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charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: When trying to test my CONFIG_IO_STRICT_DEVMEM changes I realized they do nothing for i915. Because i915 doesn't request any regions, like pretty much all drm pci drivers. I guess this is some very old remnants from the userspace modesetting days, when we wanted to co-exist with the fbdev driver. Which usually requested these resources. But makes me wonder why the pci subsystem doesn't just request resource automatically when we map a bar and a pci driver is bound? Knowledge about which pci bars we need kludged together from intel_uncore.c and intel_gtt.c from i915 and intel-gtt.c over in the fake agp driver. Signed-off-by: Daniel Vetter Cc: Jason Gunthorpe Cc: Kees Cook Cc: Dan Williams Cc: Andrew Morton Cc: John Hubbard Cc: J=C3=A9r=C3=B4me Glisse Cc: Jan Kara Cc: Dan Williams Cc: linux-mm@kvack.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-media@vger.kernel.org Cc: Bjorn Helgaas Cc: linux-pci@vger.kernel.org --- drivers/gpu/drm/i915/intel_uncore.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/i= ntel_uncore.c index 54e201fdeba4..ce39049d8919 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1692,10 +1692,13 @@ static int uncore_mmio_setup(struct intel_uncore = *uncore) struct pci_dev *pdev =3D i915->drm.pdev; int mmio_bar; int mmio_size; + int bar_selection; + int ret; =20 mmio_bar =3D IS_GEN(i915, 2) ? 1 : 0; + bar_selection =3D BIT (2) | BIT(mmio_bar); /* - * Before gen4, the registers and the GTT are behind different BARs. + * On gen3 the registers and the GTT are behind different BARs. * However, from gen4 onwards, the registers and the GTT are shared * in the same BAR, so we want to restrict this ioremap from * clobbering the GTT which we want ioremap_wc instead. Fortunately, @@ -1703,6 +1706,8 @@ static int uncore_mmio_setup(struct intel_uncore *u= ncore) * generations up to Ironlake. * For dgfx chips register range is expanded to 4MB. */ + if (INTEL_GEN(i915) =3D=3D 3) + bar_selection |=3D BIT(3); if (INTEL_GEN(i915) < 5) mmio_size =3D 512 * 1024; else if (IS_DGFX(i915)) @@ -1710,8 +1715,15 @@ static int uncore_mmio_setup(struct intel_uncore *= uncore) else mmio_size =3D 2 * 1024 * 1024; =20 + ret =3D pci_request_selected_regions(pdev, bar_selection, "i915"); + if (ret < 0) { + drm_err(&i915->drm, "failed to request pci bars\n"); + return ret; + } + uncore->regs =3D pci_iomap(pdev, mmio_bar, mmio_size); if (uncore->regs =3D=3D NULL) { + pci_release_selected_regions(pdev, bar_selection); drm_err(&i915->drm, "failed to map registers\n"); return -EIO; } @@ -1721,9 +1733,18 @@ static int uncore_mmio_setup(struct intel_uncore *= uncore) =20 static void uncore_mmio_cleanup(struct intel_uncore *uncore) { - struct pci_dev *pdev =3D uncore->i915->drm.pdev; + struct drm_i915_private *i915 =3D uncore->i915; + struct pci_dev *pdev =3D i915->drm.pdev; + int mmio_bar; + int bar_selection; + + mmio_bar =3D IS_GEN(i915, 2) ? 1 : 0; + bar_selection =3D BIT (2) | BIT(mmio_bar); + if (INTEL_GEN(i915) =3D=3D 3) + bar_selection |=3D BIT(3); =20 pci_iounmap(pdev, uncore->regs); + pci_release_selected_regions(pdev, bar_selection); } =20 void intel_uncore_init_early(struct intel_uncore *uncore, --=20 2.28.0