Re: [PATCH] MIPS: clean up CONFIG_MIPS_PGD_C0_CONTEXT handling

[Thomas Bogendoerfer <tsbogend@alpha.franken.de>]

On Sat, Mar 13, 2021 at 09:39:27AM +0800, Huang Pei wrote:
> +. LOONGSON64 use 0x98xx_xxxx_xxxx_xxxx as xphys cached, instread of
> 0xa8xx_xxxx_xxxx_xxxx
> 
> +. let CONFIG_MIPS_PGD_C0_CONTEXT depend on 64bit
> 
> +. cast CAC_BASE into u64 to silence warning on MIPS32
> 
> CP0 Context has enough room for wraping pgd into its 41-bit PTEBase field.
> 
> +. For XPHYS, the trick is that pgd is 4kB aligned, and the PABITS <= 53,
> only save 53 - 12 = 41 bits, aka :
> 
>    bit[63:59] | 0000 00 |  bit[53:12] | 0000 0000 0000
> 
> +. for CKSEG0, only save 29 - 12 = 17 bits
> 
> when switching pgd, only need to save bit[53:12] or bit[28:12] into
> CP0 Context's bit[63:23], see folling asm generated at run time
> 
> tlbmiss_handler_setup_pgd:
> 	.set	push
> 	.set	noreorder
> 
> 	dsra	a2, a0, 29
> 	move	a3, a0
> 	dins	a0, zero, 29, 35
> 	daddiu	a2, a2, 4	//for CKSEG0, a2 from 0xfffffffffffffffc
> 				//into 0
> 
> 	movn	a0, a3, a2
> 	dsll	a0, a0, 11
> 	jr	ra
> 	dmtc0	a0, CP0_CONTEXT
> 
> 	.set	pop
> 
> when using it on page walking
> 
> 	dmfc0	k0, CP0_CONTEXT
> 	dins	k0, zero, 0, 23	         // zero badv2
> 	ori	k0, k0, (CAC_BASE >> 53) // *prefix* with bit[63:59]
> 	drotr	k0, k0, 11		 // kick it in the right place
> 
> Signed-off-by: Huang Pei <huangpei@loongson.cn>
> ---
>  arch/mips/Kconfig    | 3 ++-
>  arch/mips/mm/tlbex.c | 9 +++++----
>  2 files changed, 7 insertions(+), 5 deletions(-)

applied to mips-next.

Thomas.

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