From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EDA8C4320A for ; Thu, 19 Aug 2021 09:19:31 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id A015461131 for ; Thu, 19 Aug 2021 09:19:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org A015461131 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvack.org Received: by kanga.kvack.org (Postfix) id 1154F6B006C; Thu, 19 Aug 2021 05:19:30 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 0C5866B0071; Thu, 19 Aug 2021 05:19:30 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id F1CFD8D0001; Thu, 19 Aug 2021 05:19:29 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0015.hostedemail.com [216.40.44.15]) by kanga.kvack.org (Postfix) with ESMTP id DA7746B006C for ; Thu, 19 Aug 2021 05:19:29 -0400 (EDT) Received: from smtpin06.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay05.hostedemail.com (Postfix) with ESMTP id 6D3831820128D for ; Thu, 19 Aug 2021 09:19:29 +0000 (UTC) X-FDA: 78491282058.06.E6B7D03 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by imf03.hostedemail.com (Postfix) with ESMTP id 26F0130039BA for ; Thu, 19 Aug 2021 09:19:29 +0000 (UTC) Received: by mail.kernel.org (Postfix) with ESMTPSA id 4BCD8610FE; Thu, 19 Aug 2021 09:19:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1629364768; bh=J3jp7ZOkmWaO9tQLpZ1zOGBcgY8a5WTZo9zNRh3HUAY=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=XvDObTH1MOu+er8ygQ8tnVIPybva2pjBx62TiiFqpRZawleBeoaabGzphlQV2XsW2 9/xB5KBQg7OmeqW1nAvJ9mGrTkdCSYw7/rl3wdisllQdqKYIs7wsxBuv027Rm/itMr /+I27VJYxY0h5GUzb6rZ9WbZsqBCpFxmE8TQvgkjhv+3QmtGo9ukC2YWUfUnwdwcVN IapLyOnD8Uvf07weYeBwDtjxMkbUq18oBYNK6TUAKRPz+rezCcU6MzyZDM03WkGdQ6 /s1/+tK/QTFEq4MapPLC6diOyaVXvmjC0Kd5OlT3QW2OPkXwUrz7YjiVq3A/a2xqvF jLZ2XG3l97IzQ== Date: Thu, 19 Aug 2021 10:19:23 +0100 From: Will Deacon To: Yu Zhao Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org, Hillf Danton , page-reclaim@google.com Subject: Re: [PATCH v4 01/11] mm: x86, arm64: add arch_has_hw_pte_young() Message-ID: <20210819091923.GA15467@willie-the-truck> References: <20210818063107.2696454-1-yuzhao@google.com> <20210818063107.2696454-2-yuzhao@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210818063107.2696454-2-yuzhao@google.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-Rspamd-Queue-Id: 26F0130039BA Authentication-Results: imf03.hostedemail.com; dkim=pass header.d=kernel.org header.s=k20201202 header.b=XvDObTH1; dmarc=pass (policy=none) header.from=kernel.org; spf=pass (imf03.hostedemail.com: domain of will@kernel.org designates 198.145.29.99 as permitted sender) smtp.mailfrom=will@kernel.org X-Rspamd-Server: rspam04 X-Stat-Signature: 9u9649g48n1o97m3qaiwfux3s61ga89x X-HE-Tag: 1629364769-972329 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Wed, Aug 18, 2021 at 12:30:57AM -0600, Yu Zhao wrote: > Some architectures set the accessed bit in PTEs automatically, e.g., > x86, and arm64 v8.2 and later. On architectures that do not have this > capability, clearing the accessed bit in a PTE triggers a page fault > following the TLB miss. > > Being aware of this capability can help make better decisions, i.e., > whether to limit the size of each batch of PTEs and the burst of > batches when clearing the accessed bit. > > Signed-off-by: Yu Zhao > --- > arch/arm64/include/asm/cpufeature.h | 19 ++++++------------- > arch/arm64/include/asm/pgtable.h | 10 ++++------ > arch/arm64/kernel/cpufeature.c | 19 +++++++++++++++++++ > arch/arm64/mm/proc.S | 12 ------------ > arch/arm64/tools/cpucaps | 1 + > arch/x86/include/asm/pgtable.h | 6 +++--- > include/linux/pgtable.h | 12 ++++++++++++ > mm/memory.c | 14 +------------- > 8 files changed, 46 insertions(+), 47 deletions(-) Please cc linux-arm-kernel and the maintainers on arm64 patches. > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h > index 9bb9d11750d7..2020b9e818c8 100644 > --- a/arch/arm64/include/asm/cpufeature.h > +++ b/arch/arm64/include/asm/cpufeature.h > @@ -776,6 +776,12 @@ static inline bool system_supports_tlb_range(void) > cpus_have_const_cap(ARM64_HAS_TLB_RANGE); > } > > +/* Check whether hardware update of the Access flag is supported. */ > +static inline bool system_has_hw_af(void) > +{ > + return IS_ENABLED(CONFIG_ARM64_HW_AFDBM) && cpus_have_const_cap(ARM64_HW_AF); > +} How accurate does this need to be? Heterogeneous (big/little) systems are very common on arm64, so the existing code enables hardware access flag unconditionally on CPUs that support it, meaning we could end up running on a system where some CPUs have hardware update and others do not. With your change, we only enable hardware access flag if _all_ CPUs support it (and furthermore, we prevent late onlining of CPUs without the feature if was detected at boot). This sacrifices a lot of flexibility, particularly if we end up tackling CPU errata in this area in future, and it's not clear that it's really required for what you're trying to do. Will