From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6773C433F5 for ; Fri, 28 Jan 2022 08:28:10 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 5A80B6B0071; Fri, 28 Jan 2022 03:28:10 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 558AB6B0072; Fri, 28 Jan 2022 03:28:10 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 41FB86B0073; Fri, 28 Jan 2022 03:28:10 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (relay028.a.hostedemail.com [64.99.140.28]) by kanga.kvack.org (Postfix) with ESMTP id 335876B0071 for ; Fri, 28 Jan 2022 03:28:10 -0500 (EST) Received: from smtpin02.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay02.hostedemail.com (Postfix) with ESMTP id DD97D22BB4 for ; Fri, 28 Jan 2022 08:28:09 +0000 (UTC) X-FDA: 79079018298.02.AD6A3F3 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by imf17.hostedemail.com (Postfix) with ESMTP id 2FA964000E for ; Fri, 28 Jan 2022 08:28:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643358489; x=1674894489; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=0yiNsJ1tR7PSgwRrBaP+3x76s+wLRvU9DacOc8key2s=; b=LfQXG4Q0WtudPysBTbYgQA2vsWiL0TvuAzkA9kezFeoGIb3PxZoO/LN1 85+QVRqsS0SWTMTCUZmuYEcfXHScDgQljZTd+nXwjzsjsrImnBgoXzeQI UOAr8T+1ZcwZvS81zKIkFI333/5+lqwx0vTETwcHxSt5g4rF0+LvITYqi r03c90LNh4mnQjwO3wG1N+vI8TUdLDtSq5SFbtf+1p2EkLhmKNymVjbKX sAhFitgSZX7boJGLX8wkZ2eb1Vy+GNNlQBzl5FUF/PrmmtSlHG3xcZ00z MLUuEfM2EZHD4pNixE3Vml/u1RVq8GVng+9SPJe42dLfpGDRhwuxVYt6T w==; X-IronPort-AV: E=McAfee;i="6200,9189,10240"; a="234454506" X-IronPort-AV: E=Sophos;i="5.88,323,1635231600"; d="scan'208";a="234454506" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 00:28:07 -0800 X-IronPort-AV: E=Sophos;i="5.88,323,1635231600"; d="scan'208";a="697019586" Received: from yhuang6-desk2.sh.intel.com ([10.239.13.11]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 00:28:04 -0800 From: Huang Ying To: Peter Zijlstra , Mel Gorman Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org, Feng Tang , Huang Ying , Andrew Morton , Michal Hocko , Rik van Riel , Mel Gorman , Dave Hansen , Yang Shi , Zi Yan , Wei Xu , osalvador , Shakeel Butt , Hasan Al Maruf Subject: [PATCH -V11 0/3] NUMA balancing: optimize memory placement for memory tiering system Date: Fri, 28 Jan 2022 16:27:48 +0800 Message-Id: <20220128082751.593478-1-ying.huang@intel.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 2FA964000E X-Rspam-User: nil Authentication-Results: imf17.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=LfQXG4Q0; dmarc=pass (policy=none) header.from=intel.com; spf=none (imf17.hostedemail.com: domain of ying.huang@intel.com has no SPF policy when checking 134.134.136.20) smtp.mailfrom=ying.huang@intel.com X-Stat-Signature: d4cerh4qqfcrcmd3fcahymf8z3g9kjeq X-Rspamd-Server: rspam08 X-HE-Tag: 1643358488-795806 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: The changes since the last post are as follows, - Rebased on v5.17-rc1 - Remove [4-6] from the original patchset to make it easier to be reviewed. - Change the additional promotion watermark to be the high watermark / 4. -- With the advent of various new memory types, some machines will have multiple types of memory, e.g. DRAM and PMEM (persistent memory). The memory subsystem of these machines can be called memory tiering system, because the performance of the different types of memory are different. After commit c221c0b0308f ("device-dax: "Hotplug" persistent memory for use like normal RAM"), the PMEM could be used as the cost-effective volatile memory in separate NUMA nodes. In a typical memory tiering system, there are CPUs, DRAM and PMEM in each physical NUMA node. The CPUs and the DRAM will be put in one logical node, while the PMEM will be put in another (faked) logical node. To optimize the system overall performance, the hot pages should be placed in DRAM node. To do that, we need to identify the hot pages in the PMEM node and migrate them to DRAM node via NUMA migration. In the original NUMA balancing, there are already a set of existing mechanisms to identify the pages recently accessed by the CPUs in a node and migrate the pages to the node. So we can reuse these mechanisms to build the mechanisms to optimize the page placement in the memory tiering system. This is implemented in this patchset. At the other hand, the cold pages should be placed in PMEM node. So, we also need to identify the cold pages in the DRAM node and migrate them to PMEM node. In commit 26aa2d199d6f ("mm/migrate: demote pages during reclaim"), a mechanism to demote the cold DRAM pages to PMEM node under memory pressure is implemented. Based on that, the cold DRAM pages can be demoted to PMEM node proactively to free some memory space on DRAM node to accommodate the promoted hot PMEM pages. This is implemented in this patchset too. We have tested the solution with the pmbench memory accessing benchmark with the 80:20 read/write ratio and the Gauss access address distribution on a 2 socket Intel server with Optane DC Persistent Memory Model. The test results shows that the pmbench score can improve up to 95.9%. Changelog: v11: - Rebased on v5.17-rc1 - Remove [4-6] from the original patchset to make it easier to be reviewed. - Change the additional promotion watermark to be the high watermark / 4. v10: - Rebased on v5.16-rc1 - Revise error processing for [1/6] (promotion counter) per Yang's comments - Add sysctl document for [2/6] (optimize page placement) - Reset threshold adjustment state when disable/enable tiering mode - Reset threshold when workload transition is detected. v9: - Rebased on v5.15-rc4 - Make "add promotion counter" the first patch per Yang's comments v8: - Rebased on v5.15-rc1 - Make user-specified threshold take effect sooner v7: - Rebased on the mmots tree of 2021-07-15. - Some minor fixes. v6: - Rebased on the latest page demotion patchset. (which bases on v5.11) v5: - Rebased on the latest page demotion patchset. (which bases on v5.10) v4: - Rebased on the latest page demotion patchset. (which bases on v5.9-rc6) - Add page promotion counter. v3: - Move the rate limit control as late as possible per Mel Gorman's comments. - Revise the hot page selection implementation to store page scan time in struct page. - Code cleanup. - Rebased on the latest page demotion patchset. v2: - Addressed comments for V1. - Rebased on v5.5. Best Regards, Huang, Ying