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David Alan Gilbert" , , , , , Brijesh Singh Subject: [PATCH v10 32/45] x86/compressed/64: Add support for SEV-SNP CPUID table in #VC handlers Date: Wed, 9 Feb 2022 12:10:26 -0600 Message-ID: <20220209181039.1262882-33-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220209181039.1262882-1-brijesh.singh@amd.com> References: <20220209181039.1262882-1-brijesh.singh@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 28c7b3ac-45d0-42aa-42d9-08d9ebf7b88f X-MS-TrafficTypeDiagnostic: CH2PR12MB3845:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3383; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: XSl7LV7+0+Oan3uOCNNnKEeY0CLfpdzhGt8q0lujpX4WBxlES9Mkehvhqp6dbHNP40Jzl1udTOvXz2HptWPRSEg3w53Viynb4euhFVJBxGXnNJ0BY/lli7BWqvkPO39BbVHU1I33/ogsm23fvutCvkCJhgFuHivpHIJl5Ldeudic4oTEcAouFf49MovxP0LVUfOWzvUgdNiVJZCkpc08Svpm279R5fd7EqJsMujsQLaZyvXF4+k7Df/JFaDaBc5YNET/kopOke7G1BwaFVgEibGSBUj8zSlChzj45zNirbEwN59s4gox0zkf7SsehmSCPZFU17xIub5Hm/E5tdFFmBxkeRX58iTnT/ZoNgru3r/Zqrq3OXPUnPxBQqMIij3dJG6IEx8TyhTXn1qTOTRgMOwiEll9lGb/tkgTkiEap9DYDYSNZciF8WcAEYtJAW5qEfOlWz1tEBk+nWBkrC/vqJ0vkiRkj+urMqf3q4kYHDQ+4Fe8UTzFRd4ej5c9fKqG5NnL+6D9rKy6aYlOzDJdjAbOtm3AUTbeDsIZhWbumLeQttq78mrM5roN4WnSG6bt2HRTnH8xjSUsKPJoQh9JjumCoBplnQW7m7VCKavPHBHdFUzDUsy+m3sYf2qzV7tDPgoMO0SN4CMuMFm9mx5jkdRgbRZ/IoSvD1mp1bvDs1HJs4ekpuT7NCOs0ddSrsxttn6rRmOjCfP4TPxQhTA24xh2+Gl1G/QsrxJjGU5TcAg= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(4326008)(70206006)(8676002)(70586007)(81166007)(47076005)(5660300002)(8936002)(54906003)(110136005)(316002)(44832011)(36756003)(2906002)(7416002)(7406005)(30864003)(426003)(82310400004)(336012)(7696005)(508600001)(186003)(16526019)(2616005)(1076003)(26005)(356005)(83380400001)(40460700003)(36860700001)(86362001)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Feb 2022 18:12:23.4856 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 28c7b3ac-45d0-42aa-42d9-08d9ebf7b88f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT018.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB3845 X-Rspamd-Queue-Id: D2B8C180008 X-Stat-Signature: 9ym9et58z7mkiforn7rwhq7k1azscr4o X-Rspam-User: Authentication-Results: imf16.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=jc+vBUEJ; spf=pass (imf16.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.244.67 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-Rspamd-Server: rspam05 X-HE-Tag: 1644430347-605383 Content-Transfer-Encoding: quoted-printable X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Michael Roth CPUID instructions generate a #VC exception for SEV-ES/SEV-SNP guests, for which early handlers are currently set up to handle. In the case of SEV-SNP, guests can use a configurable location in guest memory that has been pre-populated with a firmware-validated CPUID table to look up the relevant CPUID values rather than requesting them from hypervisor via a VMGEXIT. Add the various hooks in the #VC handlers to allow CPUID instructions to be handled via the table. The code to actually configure/enable the table will be added in a subsequent commit. Signed-off-by: Michael Roth Signed-off-by: Brijesh Singh --- arch/x86/include/asm/sev-common.h | 2 + arch/x86/kernel/sev-shared.c | 324 ++++++++++++++++++++++++++++++ 2 files changed, 326 insertions(+) diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev= -common.h index e9b6815b3b3d..0759af9b1acf 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -152,6 +152,8 @@ struct snp_psc_desc { #define GHCB_TERM_PSC 1 /* Page State Change failure */ #define GHCB_TERM_PVALIDATE 2 /* Pvalidate failure */ #define GHCB_TERM_NOT_VMPL0 3 /* SNP guest is not running at VMPL-0 */ +#define GHCB_TERM_CPUID 4 /* CPUID-validation failure */ +#define GHCB_TERM_CPUID_HV 5 /* CPUID failure during hypervisor fallbac= k */ =20 #define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK) =20 diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index b4d5558c9d0a..0f1375164ff0 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -24,6 +24,36 @@ struct cpuid_leaf { u32 edx; }; =20 +/* + * Individual entries of the SNP CPUID table, as defined by the SNP + * Firmware ABI, Revision 0.9, Section 7.1, Table 14. + */ +struct snp_cpuid_fn { + u32 eax_in; + u32 ecx_in; + u64 xcr0_in; + u64 xss_in; + u32 eax; + u32 ebx; + u32 ecx; + u32 edx; + u64 __reserved; +} __packed; + +/* + * SNP CPUID table, as defined by the SNP Firmware ABI, Revision 0.9, + * Section 8.14.2.6. Also noted there is the SNP firmware-enforced limit + * of 64 entries per CPUID table. + */ +#define SNP_CPUID_COUNT_MAX 64 + +struct snp_cpuid_table { + u32 count; + u32 __reserved1; + u64 __reserved2; + struct snp_cpuid_fn fn[SNP_CPUID_COUNT_MAX]; +} __packed; + /* * Since feature negotiation related variables are set early in the boot * process they must reside in the .data section so as not to be zeroed @@ -33,6 +63,19 @@ struct cpuid_leaf { */ static u16 ghcb_version __ro_after_init; =20 +/* Copy of the SNP firmware's CPUID page. */ +static struct snp_cpuid_table cpuid_table_copy __ro_after_init; + +/* + * These will be initialized based on CPUID table so that non-present + * all-zero leaves (for sparse tables) can be differentiated from + * invalid/out-of-range leaves. This is needed since all-zero leaves + * still need to be post-processed. + */ +static u32 cpuid_std_range_max __ro_after_init; +static u32 cpuid_hyp_range_max __ro_after_init; +static u32 cpuid_ext_range_max __ro_after_init; + static bool __init sev_es_check_cpu_features(void) { if (!has_cpuflag(X86_FEATURE_RDRAND)) { @@ -242,6 +285,252 @@ static int sev_cpuid_hv(struct cpuid_leaf *leaf) return ret; } =20 +/* + * This may be called early while still running on the initial identity + * mapping. Use RIP-relative addressing to obtain the correct address + * while running with the initial identity mapping as well as the + * switch-over to kernel virtual addresses later. + */ +static const struct snp_cpuid_table *snp_cpuid_get_table(void) +{ + void *ptr; + + asm ("lea cpuid_table_copy(%%rip), %0" + : "=3Dr" (ptr) + : "p" (&cpuid_table_copy)); + + return ptr; +} + +/* + * The SNP Firmware ABI, Revision 0.9, Section 7.1, details the use of + * XCR0_IN and XSS_IN to encode multiple versions of 0xD subfunctions 0 + * and 1 based on the corresponding features enabled by a particular + * combination of XCR0 and XSS registers so that a guest can look up the + * version corresponding to the features currently enabled in its XCR0/X= SS + * registers. The only values that differ between these versions/table + * entries is the enabled XSAVE area size advertised via EBX. + * + * While hypervisors may choose to make use of this support, it is more + * robust/secure for a guest to simply find the entry corresponding to t= he + * base/legacy XSAVE area size (XCR0=3D1 or XCR0=3D3), and then calculat= e the + * XSAVE area size using subfunctions 2 through 64, as documented in APM + * Volume 3, Rev 3.31, Appendix E.3.8, which is what is done here. + * + * Since base/legacy XSAVE area size is documented as 0x240, use that va= lue + * directly rather than relying on the base size in the CPUID table. + * + * Return: XSAVE area size on success, 0 otherwise. + */ +static u32 snp_cpuid_calc_xsave_size(u64 xfeatures_en, bool compacted) +{ + const struct snp_cpuid_table *cpuid_table =3D snp_cpuid_get_table(); + u64 xfeatures_found =3D 0; + u32 xsave_size =3D 0x240; + int i; + + for (i =3D 0; i < cpuid_table->count; i++) { + const struct snp_cpuid_fn *e =3D &cpuid_table->fn[i]; + + if (!(e->eax_in =3D=3D 0xD && e->ecx_in > 1 && e->ecx_in < 64)) + continue; + if (!(xfeatures_en & (BIT_ULL(e->ecx_in)))) + continue; + if (xfeatures_found & (BIT_ULL(e->ecx_in))) + continue; + + xfeatures_found |=3D (BIT_ULL(e->ecx_in)); + + if (compacted) + xsave_size +=3D e->eax; + else + xsave_size =3D max(xsave_size, e->eax + e->ebx); + } + + /* + * Either the guest set unsupported XCR0/XSS bits, or the corresponding + * entries in the CPUID table were not present. This is not a valid + * state to be in. + */ + if (xfeatures_found !=3D (xfeatures_en & GENMASK_ULL(63, 2))) + return 0; + + return xsave_size; +} + +static bool +snp_cpuid_get_validated_func(struct cpuid_leaf *leaf) +{ + const struct snp_cpuid_table *cpuid_table =3D snp_cpuid_get_table(); + int i; + + for (i =3D 0; i < cpuid_table->count; i++) { + const struct snp_cpuid_fn *e =3D &cpuid_table->fn[i]; + + if (e->eax_in !=3D leaf->fn) + continue; + + if (cpuid_function_is_indexed(leaf->fn) && e->ecx_in !=3D leaf->subfn) + continue; + + /* + * For 0xD subfunctions 0 and 1, only use the entry corresponding + * to the base/legacy XSAVE area size (XCR0=3D1 or XCR0=3D3, XSS=3D0). + * See the comments above snp_cpuid_calc_xsave_size() for more + * details. + */ + if (e->eax_in =3D=3D 0xD && (e->ecx_in =3D=3D 0 || e->ecx_in =3D=3D 1)= ) + if (!(e->xcr0_in =3D=3D 1 || e->xcr0_in =3D=3D 3) || e->xss_in) + continue; + + leaf->eax =3D e->eax; + leaf->ebx =3D e->ebx; + leaf->ecx =3D e->ecx; + leaf->edx =3D e->edx; + + return true; + } + + return false; +} + +static void snp_cpuid_hv(struct cpuid_leaf *leaf) +{ + if (sev_cpuid_hv(leaf)) + sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_CPUID_HV); +} + +static int snp_cpuid_postprocess(struct cpuid_leaf *leaf) +{ + struct cpuid_leaf leaf_hv =3D *leaf; + + switch (leaf->fn) { + case 0x1: + snp_cpuid_hv(&leaf_hv); + + /* initial APIC ID */ + leaf->ebx =3D (leaf_hv.ebx & GENMASK(31, 24)) | (leaf->ebx & GENMASK(2= 3, 0)); + /* APIC enabled bit */ + leaf->edx =3D (leaf_hv.edx & BIT(9)) | (leaf->edx & ~BIT(9)); + + /* OSXSAVE enabled bit */ + if (native_read_cr4() & X86_CR4_OSXSAVE) + leaf->ecx |=3D BIT(27); + break; + case 0x7: + /* OSPKE enabled bit */ + leaf->ecx &=3D ~BIT(4); + if (native_read_cr4() & X86_CR4_PKE) + leaf->ecx |=3D BIT(4); + break; + case 0xB: + leaf_hv.subfn =3D 0; + snp_cpuid_hv(&leaf_hv); + + /* extended APIC ID */ + leaf->edx =3D leaf_hv.edx; + break; + case 0xD: { + bool compacted =3D false; + u64 xcr0 =3D 1, xss =3D 0; + u32 xsave_size; + + if (leaf->subfn !=3D 0 && leaf->subfn !=3D 1) + return 0; + + if (native_read_cr4() & X86_CR4_OSXSAVE) + xcr0 =3D xgetbv(XCR_XFEATURE_ENABLED_MASK); + if (leaf->subfn =3D=3D 1) { + /* Get XSS value if XSAVES is enabled. */ + if (leaf->eax & BIT(3)) { + unsigned long lo, hi; + + asm volatile("rdmsr" : "=3Da" (lo), "=3Dd" (hi) + : "c" (MSR_IA32_XSS)); + xss =3D (hi << 32) | lo; + } + + /* + * The PPR and APM aren't clear on what size should be + * encoded in 0xD:0x1:EBX when compaction is not enabled + * by either XSAVEC (feature bit 1) or XSAVES (feature + * bit 3) since SNP-capable hardware has these feature + * bits fixed as 1. KVM sets it to 0 in this case, but + * to avoid this becoming an issue it's safer to simply + * treat this as unsupported for SNP guests. + */ + if (!(leaf->eax & (BIT(1) | BIT(3)))) + return -EINVAL; + + compacted =3D true; + } + + xsave_size =3D snp_cpuid_calc_xsave_size(xcr0 | xss, compacted); + if (!xsave_size) + return -EINVAL; + + leaf->ebx =3D xsave_size; + } + break; + case 0x8000001E: + snp_cpuid_hv(&leaf_hv); + + /* extended APIC ID */ + leaf->eax =3D leaf_hv.eax; + /* compute ID */ + leaf->ebx =3D (leaf->ebx & GENMASK(31, 8)) | (leaf_hv.ebx & GENMASK(7,= 0)); + /* node ID */ + leaf->ecx =3D (leaf->ecx & GENMASK(31, 8)) | (leaf_hv.ecx & GENMASK(7,= 0)); + break; + default: + /* No fix-ups needed, use values as-is. */ + break; + } + + return 0; +} + +/* + * Returns -EOPNOTSUPP if feature not enabled. Any other non-zero return= value + * should be treated as fatal by caller. + */ +static int snp_cpuid(struct cpuid_leaf *leaf) +{ + const struct snp_cpuid_table *cpuid_table =3D snp_cpuid_get_table(); + + if (!cpuid_table->count) + return -EOPNOTSUPP; + + if (!snp_cpuid_get_validated_func(leaf)) { + /* + * Some hypervisors will avoid keeping track of CPUID entries + * where all values are zero, since they can be handled the + * same as out-of-range values (all-zero). This is useful here + * as well as it allows virtually all guest configurations to + * work using a single SNP CPUID table. + * + * To allow for this, there is a need to distinguish between + * out-of-range entries and in-range zero entries, since the + * CPUID table entries are only a template that may need to be + * augmented with additional values for things like + * CPU-specific information during post-processing. So if it's + * not in the table, set the values to zero. Then, if they are + * within a valid CPUID range, proceed with post-processing + * using zeros as the initial values. Otherwise, skip + * post-processing and just return zeros immediately. + */ + leaf->eax =3D leaf->ebx =3D leaf->ecx =3D leaf->edx =3D 0; + + /* Skip post-processing for out-of-range zero leafs. */ + if (!(leaf->fn <=3D cpuid_std_range_max || + (leaf->fn >=3D 0x40000000 && leaf->fn <=3D cpuid_hyp_range_max) = || + (leaf->fn >=3D 0x80000000 && leaf->fn <=3D cpuid_ext_range_max))= ) + return 0; + } + + return snp_cpuid_postprocess(leaf); +} + /* * Boot VC Handler - This is the first VC handler during boot, there is = no GHCB * page yet, so it only supports the MSR based communication with the @@ -252,6 +541,7 @@ void __init do_vc_no_ghcb(struct pt_regs *regs, unsig= ned long exit_code) unsigned int subfn =3D lower_bits(regs->cx, 32); unsigned int fn =3D lower_bits(regs->ax, 32); struct cpuid_leaf leaf; + int ret; =20 /* Only CPUID is supported via MSR protocol */ if (exit_code !=3D SVM_EXIT_CPUID) @@ -259,9 +549,18 @@ void __init do_vc_no_ghcb(struct pt_regs *regs, unsi= gned long exit_code) =20 leaf.fn =3D fn; leaf.subfn =3D subfn; + + ret =3D snp_cpuid(&leaf); + if (!ret) + goto cpuid_done; + + if (ret !=3D -EOPNOTSUPP) + goto fail; + if (sev_cpuid_hv(&leaf)) goto fail; =20 +cpuid_done: regs->ax =3D leaf.eax; regs->bx =3D leaf.ebx; regs->cx =3D leaf.ecx; @@ -556,12 +855,37 @@ static enum es_result vc_handle_ioio(struct ghcb *g= hcb, struct es_em_ctxt *ctxt) return ret; } =20 +static int vc_handle_cpuid_snp(struct pt_regs *regs) +{ + struct cpuid_leaf leaf; + int ret; + + leaf.fn =3D regs->ax; + leaf.subfn =3D regs->cx; + ret =3D snp_cpuid(&leaf); + if (!ret) { + regs->ax =3D leaf.eax; + regs->bx =3D leaf.ebx; + regs->cx =3D leaf.ecx; + regs->dx =3D leaf.edx; + } + + return ret; +} + static enum es_result vc_handle_cpuid(struct ghcb *ghcb, struct es_em_ctxt *ctxt) { struct pt_regs *regs =3D ctxt->regs; u32 cr4 =3D native_read_cr4(); enum es_result ret; + int snp_cpuid_ret; + + snp_cpuid_ret =3D vc_handle_cpuid_snp(regs); + if (!snp_cpuid_ret) + return ES_OK; + if (snp_cpuid_ret !=3D -EOPNOTSUPP) + return ES_VMM_ERROR; =20 ghcb_set_rax(ghcb, regs->ax); ghcb_set_rcx(ghcb, regs->cx); --=20 2.25.1