From: Bharata B Rao <bharata@amd.com>
To: <linux-kernel@vger.kernel.org>
Cc: <linux-mm@kvack.org>, <x86@kernel.org>,
<kirill.shutemov@linux.intel.com>, <tglx@linutronix.de>,
<mingo@redhat.com>, <bp@alien8.de>, <dave.hansen@linux.intel.com>,
<catalin.marinas@arm.com>, <will@kernel.org>, <shuah@kernel.org>,
<oleg@redhat.com>, <ananth.narayan@amd.com>,
"Bharata B Rao" <bharata@amd.com>
Subject: [RFC PATCH v0 3/6] x86: Enable Upper Address Ignore(UAI) feature
Date: Thu, 10 Mar 2022 16:45:42 +0530 [thread overview]
Message-ID: <20220310111545.10852-4-bharata@amd.com> (raw)
In-Reply-To: <20220310111545.10852-1-bharata@amd.com>
UAI feature is enabled by setting bit 20 in EFER MSR.
Signed-off-by: Bharata B Rao <bharata@amd.com>
---
arch/x86/include/asm/msr-index.h | 2 ++
arch/x86/kernel/setup.c | 8 ++++++++
2 files changed, 10 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index a4a39c3e0f19..ce763952278f 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -30,6 +30,7 @@
#define _EFER_SVME 12 /* Enable virtualization */
#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
+#define _EFER_UAI 20 /* Enable Upper Address Ignore */
#define EFER_SCE (1<<_EFER_SCE)
#define EFER_LME (1<<_EFER_LME)
@@ -38,6 +39,7 @@
#define EFER_SVME (1<<_EFER_SVME)
#define EFER_LMSLE (1<<_EFER_LMSLE)
#define EFER_FFXSR (1<<_EFER_FFXSR)
+#define EFER_UAI (1<<_EFER_UAI)
/* Intel MSRs. Some also available on other CPUs */
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index f7a132eb794d..12615b1b4af5 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -740,6 +740,12 @@ dump_kernel_offset(struct notifier_block *self, unsigned long v, void *p)
return 0;
}
+static inline void __init uai_enable(void)
+{
+ if (boot_cpu_has(X86_FEATURE_UAI))
+ msr_set_bit(MSR_EFER, _EFER_UAI);
+}
+
/*
* Determine if we were loaded by an EFI loader. If so, then we have also been
* passed the efi memmap, systab, etc., so we should use these data structures
@@ -1146,6 +1152,8 @@ void __init setup_arch(char **cmdline_p)
x86_init.paging.pagetable_init();
+ uai_enable();
+
kasan_init();
/*
--
2.25.1
next prev parent reply other threads:[~2022-03-10 11:16 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-10 11:15 [RFC PATCH v0 0/6] x86/AMD: Userspace address tagging Bharata B Rao
2022-03-10 11:15 ` [RFC PATCH v0 1/6] mm, arm64: Update PR_SET/GET_TAGGED_ADDR_CTRL interface Bharata B Rao
2022-03-10 11:15 ` [RFC PATCH v0 2/6] x86/cpufeatures: Add Upper Address Ignore(UAI) as CPU feature Bharata B Rao
2022-03-10 11:15 ` Bharata B Rao [this message]
2022-03-10 19:46 ` [RFC PATCH v0 3/6] x86: Enable Upper Address Ignore(UAI) feature Andrew Cooper
2022-03-10 22:37 ` David Laight
2022-03-10 22:46 ` Dave Hansen
2022-03-11 12:37 ` Boris Petkov
2022-03-10 11:15 ` [RFC PATCH v0 4/6] x86: Provide an implementation of untagged_addr() Bharata B Rao
2022-03-10 11:15 ` [RFC PATCH v0 5/6] x86: Untag user pointers in access_ok() Bharata B Rao
2022-03-10 11:15 ` [RFC PATCH v0 6/6] x86: Add prctl() options to control tagged user addresses ABI Bharata B Rao
2022-03-10 14:32 ` [RFC PATCH v0 0/6] x86/AMD: Userspace address tagging David Laight
2022-03-10 16:45 ` Dave Hansen
2022-03-10 17:19 ` David Laight
2022-03-11 5:42 ` Bharata B Rao
2022-03-11 8:15 ` David Laight
2022-03-11 9:11 ` Bharata B Rao
2022-03-11 9:36 ` David Laight
2022-03-11 16:51 ` Dave Hansen
2022-03-10 15:16 ` Dave Hansen
2022-03-10 15:22 ` Dave Hansen
2022-03-14 5:00 ` Bharata B Rao
2022-03-14 7:03 ` Dave Hansen
2022-03-21 22:29 ` Andy Lutomirski
2022-03-21 22:59 ` Thomas Gleixner
2022-03-22 5:31 ` David Laight
2022-03-23 7:48 ` Bharata B Rao
2022-04-01 19:25 ` Dave Hansen
2022-04-05 5:58 ` Bharata B Rao
2022-04-01 19:41 ` Andy Lutomirski
2022-04-05 8:14 ` Peter Zijlstra
2022-04-05 8:40 ` Bharata B Rao
2022-04-08 17:41 ` Catalin Marinas
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