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Tue, 1 Oct 2019 18:52:13 +0000 (UTC) Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 01 Oct 2019 11:52:12 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 01 Oct 2019 11:52:12 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 01 Oct 2019 11:52:12 -0700 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 1 Oct 2019 18:52:12 +0000 Received: from [10.110.48.28] (10.124.1.5) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 1 Oct 2019 18:52:11 +0000 Subject: Re: [PATCH v4 01/11] powerpc/mm: Adds counting method to monitor lockless pgtable walks To: Leonardo Bras , , , , , CC: Dan Williams , Arnd Bergmann , Greg Kroah-Hartman , Mahesh Salgaonkar , YueHaibing , "Nicholas Piggin" , Mike Rapoport , Keith Busch , Jason Gunthorpe , Paul Mackerras , Aneesh Kumar K.V , "Ganesh Goudar" , Thomas Gleixner , "Ira Weiny" , Andrew Morton , Allison Randal References: <20190927234008.11513-1-leonardo@linux.ibm.com> <20190927234008.11513-2-leonardo@linux.ibm.com> <4ff1e8e8-929b-9cfc-9bf8-ee88e34de888@nvidia.com> <2533a13f226a6e1fab387669b6cced2aa8d2e129.camel@linux.ibm.com> <48bf32ca-5d3e-5d69-4cd1-6720364a0d81@nvidia.com> <673bcb94b7752e086cc4133fb6cceb24394c02c0.camel@linux.ibm.com> <8534727b-72ed-b974-219e-02155bcd17a8@nvidia.com> <9cd8e83334047b9144133781be9abd25a5678f3d.camel@linux.ibm.com> X-Nvconfidentiality: public From: John Hubbard Message-ID: <28e680b6-1da4-70c6-4345-b3b2eaae48fd@nvidia.com> Date: Tue, 1 Oct 2019 11:52:11 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <9cd8e83334047b9144133781be9abd25a5678f3d.camel@linux.ibm.com> X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To DRHQMAIL107.nvidia.com (10.27.9.16) Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1569955932; bh=s7OJ3vyUFDKglDhgXI2AXIstflWFj1nOFUPZPEO0+ho=; h=X-PGP-Universal:Subject:To:CC:References:X-Nvconfidentiality:From: Message-ID:Date:User-Agent:MIME-Version:In-Reply-To: X-Originating-IP:X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=L5KPQVgw4K5sAsxAWqavK7IBZ2/JHUUGkZ1dhcO9JIOU4ubRZLaAX8XXyGTiZbtJi QPtKtq8o9CLdd7ssS55xtYSDePzWSuZe/tBCLRVCRuN9l2+LI2IU9O7+vHcU/ebTsm cO8o6M6qpuZ1IOgk4dGt5I/fu8scfYixme/z6XGHhe3R4MC0ih/ksEsgnxE+sqQLtX Vr1OfRwQHN+FXv+9NzYRk6ECtaMsFqBm/RpSI5yN/kyVUxZ3RPUcIHy8Dx9srzT+qG 2JLrZ5yCv+NUMagElRw3CSa7E8ZtaMj2nmpQ069cLxb+TktF1Etya7qzSlnBgPhhzG 10ar3rurx0i+Q== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On 10/1/19 11:39 AM, Leonardo Bras wrote: > On Mon, 2019-09-30 at 14:47 -0700, John Hubbard wrote: >> On 9/30/19 11:42 AM, Leonardo Bras wrote: >>> On Mon, 2019-09-30 at 10:57 -0700, John Hubbard wrote: ... > > I am failing to understand the issue. > I mean, smp_call_function_many() will issue a IPI to each CPU in > CPUmask and wait it to run before returning. > If interrupts are disabled (either by MSR_EE=0 or local_irq_disable), > the IPI will not run on that CPU, and the wait part will make sure to > lock the thread until the interrupts are enabled again. > > Could you please point the issue there? The biggest problem here is evidently my not knowing much about ppc. :) So if that's how it behaves, then all is well, sorry it took me a while to understand the MSR_EE=0 behavior. > >>>> Simply skipping that means that an additional mechanism is required...which >>>> btw might involve a new, ppc-specific routine, so maybe this is going to end >>>> up pretty close to what I pasted in after all... >>>>> Of course, if we really need that, we can add a bool parameter to the >>>>> function to choose about disabling/enabling irqs. >>>>>> * This is really a core mm function, so don't hide it away in arch layers. >>>>>> (If you're changing mm/ files, that's a big hint.) >>>>> >>>>> My idea here is to let the arch decide on how this 'register' is going >>>>> to work, as archs may have different needs (in powerpc for example, we >>>>> can't always disable irqs, since we may be in realmode). >> >> Yes, the tension there is that a) some things are per-arch, and b) it's easy >> to get it wrong. The commit below (d9101bfa6adc) is IMHO a perfect example of >> that. >> >> So, I would like core mm/ functions that guide the way, but the interrupt >> behavior complicates it. I think your original passing of just struct_mm >> is probably the right balance, assuming that I'm wrong about interrupts. >> > > I think, for the generic function, that including {en,dis}abling the > interrupt is fine. I mean, if disabling the interrupt is the generic > behavior, it's ok. > I will just make sure to explain that the interrupt {en,dis}abling is > part of the sync process. If an arch don't like it, it can write a > specific function that does the sync in a better way. (and defining > __HAVE_ARCH_LOCKLESS_PGTBL_WALK_COUNTER to ignore the generic function) > Tentatively, that sounds good. We still end up with the counter variable directly in struct mm_struct, and the generic function in mm/gup.c (or mm/somewhere), where it's easy to find and see what's going on. sure. thanks, -- John Hubbard NVIDIA