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Shutemov" References: <20210607055131.156184-1-aneesh.kumar@linux.ibm.com> From: "Aneesh Kumar K.V" Message-ID: <3f2b7150-eaba-e1ab-bb88-53a3510727b9@linux.ibm.com> Date: Tue, 8 Jun 2021 10:09:36 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 In-Reply-To: Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-GUID: yHmOaJINt8dkj1ABM1GO2cyw1fBaP23J X-Proofpoint-ORIG-GUID: n_ktbhxQyeSJ8-uwD-PcLxBW_JT_-ggm Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.761 definitions=2021-06-08_01:2021-06-04,2021-06-08 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 malwarescore=0 phishscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 mlxlogscore=992 clxscore=1015 priorityscore=1501 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106080030 Authentication-Results: imf06.hostedemail.com; dkim=pass header.d=ibm.com header.s=pp1 header.b=WU89kPye; dmarc=pass (policy=none) header.from=ibm.com; spf=pass (imf06.hostedemail.com: domain of aneesh.kumar@linux.ibm.com designates 148.163.158.5 as permitted sender) smtp.mailfrom=aneesh.kumar@linux.ibm.com X-Stat-Signature: 1h7p7c4hrubcheyurqihkatrbh9rq5fd X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: 2220FC00CBD7 X-HE-Tag: 1623127193-972180 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On 6/7/21 3:40 PM, Nick Piggin wrote: > On Monday, 7 June 2021, Aneesh Kumar K.V > wrote: This patchset enables MOVE_PMD/MOVE_PUD support on power. This > requires the platform to support updating higher-level page tables > without updating page table ZjQcmQRYFpfptBannerStart > This Message Is From an External Sender > This message came from outside your organization. > ZjQcmQRYFpfptBannerEnd > > > On Monday, 7 June 2021, Aneesh Kumar K.V > wrote: > > > This patchset enables MOVE_PMD/MOVE_PUD support on power. This requires > the platform to support updating higher-level page tables without > updating page table entries. This also needs to invalidate the Page Walk > Cache on architecture supporting the same. > > Changes from v6: > * Update ppc64 flush_tlb_range to invalidate page walk cache. > > > I'd really rather not do this, I'm not sure if micro bench mark captures > everything. > > Page tables coming from L2/L3 probably aren't the primary purpose or > biggest benefit of intermediate level caches. > > The situation on POWER with nest mmu (coherent accelerators) is > magnified. They have huge page walk cashes to make up for the fact they > don't have data caches for walking page tables which makes the > invalidation more painful in terms of subsequent misses, but also > latency to invalidate (can be order of microseconds whereas a page > invalidate is a couple of orders of magnitude faster). > If we are using NestMMU, we already upgrade that flush to invalidate page walk cache right? ie, if we have > PMD_SIZE range, we would upgrade the invalidate to a pid flush via flush_pid = nr_pages > tlb_single_page_flush_ceiling; and if it is PID flush if we are using NestMMU we already upgrade a RIC_FLUSH_TLB to RIC_FLUSH_ALL ? > Yes it is a deficiency of the ppc invalidation architecture, we are > aware and would like to improve it but for now those is what we have. > -aneesh