From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-f71.google.com (mail-wr1-f71.google.com [209.85.221.71]) by kanga.kvack.org (Postfix) with ESMTP id BBDEA6B000D for ; Mon, 15 Oct 2018 09:12:41 -0400 (EDT) Received: by mail-wr1-f71.google.com with SMTP id t9so13494205wrx.7 for ; Mon, 15 Oct 2018 06:12:41 -0700 (PDT) Received: from thoth.sbs.de (thoth.sbs.de. [192.35.17.2]) by mx.google.com with ESMTPS id c8-v6si8510797wrb.289.2018.10.15.06.12.38 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Oct 2018 06:12:39 -0700 (PDT) Subject: Re: [PATCH] x86/entry/32: Fix setup of CS high bits References: <1531906876-13451-1-git-send-email-joro@8bytes.org> <1531906876-13451-11-git-send-email-joro@8bytes.org> <97421241-2bc4-c3f1-4128-95b3e8a230d1@siemens.com> <35a24feb-5970-aa03-acbf-53428a159ace@web.de> From: Jan Kiszka Message-ID: <406a08c7-6199-a32d-d385-c032fb4c34d6@siemens.com> Date: Mon, 15 Oct 2018 15:08:54 +0200 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: owner-linux-mm@kvack.org List-ID: To: Andy Lutomirski Cc: Joerg Roedel , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , X86 ML , LKML , Linux-MM , Linus Torvalds , Dave Hansen , Josh Poimboeuf , Juergen Gross , Peter Zijlstra , Borislav Petkov , Jiri Kosina , Boris Ostrovsky , Brian Gerst , David Laight , Denys Vlasenko , Eduardo Valentin , Greg KH , Will Deacon , "Liguori, Anthony" , Daniel Gruss , Hugh Dickins , Kees Cook , Andrea Arcangeli On 13.10.18 17:12, Andy Lutomirski wrote: > On Sat, Oct 13, 2018 at 3:02 AM Jan Kiszka wrote: >> >> From: Jan Kiszka >> >> Even if we are not on an entry stack, we have to initialize the CS high >> bits because we are unconditionally evaluating them >> PARANOID_EXIT_TO_KERNEL_MODE. Failing to do so broke the boot on Galileo >> Gen2 and IOT2000 boards. >> >> Fixes: b92a165df17e ("x86/entry/32: Handle Entry from Kernel-Mode on Entry-Stack") >> Signed-off-by: Jan Kiszka >> --- >> arch/x86/entry/entry_32.S | 12 ++++++------ >> 1 file changed, 6 insertions(+), 6 deletions(-) >> >> diff --git a/arch/x86/entry/entry_32.S b/arch/x86/entry/entry_32.S >> index 2767c625a52c..95c94d48ecd2 100644 >> --- a/arch/x86/entry/entry_32.S >> +++ b/arch/x86/entry/entry_32.S >> @@ -389,6 +389,12 @@ >> * that register for the time this macro runs >> */ >> >> + /* >> + * Clear unused upper bits of the dword containing the word-sized CS >> + * slot in pt_regs in case hardware didn't clear it for us. >> + */ >> + andl $(0x0000ffff), PT_CS(%esp) >> + > > Please improve the comment. Since commit: > > commit 385eca8f277c4c34f361a4c3a088fd876d29ae21 > Author: Andy Lutomirski > Date: Fri Jul 28 06:00:30 2017 -0700 > > x86/asm/32: Make pt_regs's segment registers be 16 bits > > Those fields are genuinely 16 bit. So the comment should say > something like "Those high bits are used for CS_FROM_ENTRY_STACK and > CS_FROM_USER_CR3". /* * The high bits of the CS dword (__csh) are used for * CS_FROM_ENTRY_STACK and CS_FROM_USER_CR3. Clear them in case * hardware didn't do this for us. */ OK? I will send out v2 with this wording soon. > > Also, can you fold something like this in: > > diff --git a/arch/x86/entry/entry_32.S b/arch/x86/entry/entry_32.S > index 2767c625a52c..358eed8cf62a 100644 > --- a/arch/x86/entry/entry_32.S > +++ b/arch/x86/entry/entry_32.S > @@ -171,7 +171,7 @@ > ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI > .if \no_user_check == 0 > /* coming from usermode? */ > - testl $SEGMENT_RPL_MASK, PT_CS(%esp) > + testb $SEGMENT_RPL_MASK, PT_CS(%esp) > jz .Lend_\@ > .endif > /* On user-cr3? */ > Makes sense, but this looks like a separate patch to me. Jan -- Siemens AG, Corporate Technology, CT RDA IOT SES-DE Corporate Competence Center Embedded Linux