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From: Dave Hansen <dave.hansen@intel.com>
To: hpa@zytor.com, Linus Torvalds <torvalds@linux-foundation.org>,
	"Kirill A. Shutemov" <kirill@shutemov.name>
Cc: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
	Andrew Morton <akpm@linux-foundation.org>,
	the arch/x86 maintainers <x86@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>, Andi Kleen <ak@linux.intel.com>,
	Andy Lutomirski <luto@amacapital.net>,
	"linux-arch@vger.kernel.org" <linux-arch@vger.kernel.org>,
	linux-mm <linux-mm@kvack.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level paging
Date: Fri, 26 May 2017 12:23:18 -0700	[thread overview]
Message-ID: <40d58ba7-277c-6f4e-a4d7-15425d675dbf@intel.com> (raw)
In-Reply-To: <83F4880B-5D1F-4576-A9B6-7DDF4173E2E5@zytor.com>

On 05/26/2017 11:24 AM, hpa@zytor.com wrote:
> The only case where that even has any utility is for an application
> to want more than 128 TiB address space on a machine with no more
> than 64 TiB of RAM.  It is kind of a narrow use case, I think.

Doesn't more address space increase the effectiveness of ASLR?  I
thought KASLR, especially, was limited in its effectiveness because of a
lack of address space.

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  reply	other threads:[~2017-05-26 19:23 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-25 20:33 [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level paging Kirill A. Shutemov
2017-05-25 20:33 ` [PATCHv1, RFC 1/8] x86/boot/compressed/64: Detect and handle 5-level paging at boot-time Kirill A. Shutemov
2017-05-25 20:33 ` [PATCHv1, RFC 2/8] x86/mm: Make virtual memory layout movable for CONFIG_X86_5LEVEL Kirill A. Shutemov
2017-05-25 20:33 ` [PATCHv1, RFC 3/8] x86/mm: Make PGDIR_SHIFT and PTRS_PER_P4D variable Kirill A. Shutemov
2017-05-25 20:33 ` [PATCHv1, RFC 4/8] x86/mm: Handle boot-time paging mode switching at early boot Kirill A. Shutemov
2017-05-25 20:33 ` [PATCHv1, RFC 5/8] x86/mm: Fold p4d page table layer at runtime Kirill A. Shutemov
2017-05-27 15:09   ` Brian Gerst
2017-05-27 22:46     ` Kirill A. Shutemov
2017-05-27 22:56       ` Brian Gerst
2017-05-25 20:33 ` [PATCHv1, RFC 6/8] x86/mm: Replace compile-time checks for 5-level with runtime-time Kirill A. Shutemov
2017-05-25 20:33 ` [PATCHv1, RFC 7/8] x86/mm: Hacks for boot-time switching between 4- and 5-level paging Kirill A. Shutemov
2017-05-26 22:10   ` KASAN vs. " Kirill A. Shutemov
2017-05-29 10:02     ` Dmitry Vyukov
2017-05-29 11:18       ` Andrey Ryabinin
2017-05-29 11:19         ` Dmitry Vyukov
2017-05-29 11:45           ` Andrey Ryabinin
2017-05-29 12:46             ` Andrey Ryabinin
2017-06-01 14:56               ` Andrey Ryabinin
2017-07-10 12:33                 ` Kirill A. Shutemov
2017-07-10 12:43                   ` Dmitry Vyukov
2017-07-10 14:17                     ` Kirill A. Shutemov
2017-07-10 15:56                       ` Andy Lutomirski
2017-07-10 18:47                         ` Kirill A. Shutemov
2017-07-10 20:07                           ` Andy Lutomirski
2017-07-10 21:24                             ` Kirill A. Shutemov
2017-07-11  0:30                               ` Andy Lutomirski
2017-07-11 10:35                                 ` Kirill A. Shutemov
2017-07-11 15:06                                   ` Andy Lutomirski
2017-07-11 15:15                                     ` Andrey Ryabinin
2017-07-11 16:45                                       ` Andrey Ryabinin
2017-07-11 17:03                                         ` Kirill A. Shutemov
2017-07-11 17:29                                           ` Andrey Ryabinin
2017-07-11 19:05                                             ` Kirill A. Shutemov
2017-07-13 12:58                                               ` Andrey Ryabinin
2017-07-13 13:52                                                 ` Kirill A. Shutemov
2017-07-13 14:15                                                   ` Kirill A. Shutemov
2017-07-13 14:19                                                     ` Andrey Ryabinin
2017-07-24 12:13                                                       ` Kirill A. Shutemov
2017-07-24 14:07                                                         ` Andrey Ryabinin
2017-07-10 16:57                   ` Andrey Ryabinin
2017-05-25 20:33 ` [PATCHv1, RFC 8/8] x86/mm: Allow to boot without la57 if CONFIG_X86_5LEVEL=y Kirill A. Shutemov
2017-05-25 23:24 ` [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level paging Linus Torvalds
2017-05-26  0:40   ` Andy Lutomirski
2017-05-26  4:18     ` Kevin Easton
2017-05-26  7:21       ` Andy Lutomirski
2017-05-26 13:00   ` Kirill A. Shutemov
2017-05-26 13:35     ` Andi Kleen
2017-05-26 15:51     ` Linus Torvalds
2017-05-26 15:58       ` Kirill A. Shutemov
2017-05-26 16:13         ` Linus Torvalds
2017-05-26 18:24       ` hpa
2017-05-26 19:23         ` Dave Hansen [this message]
2017-05-26 19:36           ` hpa
2017-05-26 19:40     ` hpa

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