From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11114C07E95 for ; Fri, 16 Jul 2021 14:36:28 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 9C68D613FA for ; Fri, 16 Jul 2021 14:36:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9C68D613FA Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id A18F78D00F4; Fri, 16 Jul 2021 10:36:27 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 9A08A8D00EC; Fri, 16 Jul 2021 10:36:27 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 81B128D00F4; Fri, 16 Jul 2021 10:36:27 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0188.hostedemail.com [216.40.44.188]) by kanga.kvack.org (Postfix) with ESMTP id 575798D00EC for ; Fri, 16 Jul 2021 10:36:27 -0400 (EDT) Received: from smtpin15.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay04.hostedemail.com (Postfix) with ESMTP id 212F511204 for ; Fri, 16 Jul 2021 14:36:26 +0000 (UTC) X-FDA: 78368701572.15.3C9D25F Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by imf17.hostedemail.com (Postfix) with ESMTP id 7B2F3F002C9B for ; Fri, 16 Jul 2021 14:36:25 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 85233D6E; Fri, 16 Jul 2021 07:36:24 -0700 (PDT) Received: from [10.163.67.71] (unknown [10.163.67.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0809D3F774; Fri, 16 Jul 2021 07:36:20 -0700 (PDT) From: Anshuman Khandual Subject: Re: [RFC 06/10] arm64/mm: Add FEAT_LPA2 specific encoding To: Steven Price , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org Cc: akpm@linux-foundation.org, suzuki.poulose@arm.com, mark.rutland@arm.com, will@kernel.org, catalin.marinas@arm.com, maz@kernel.org, james.morse@arm.com References: <1626229291-6569-1-git-send-email-anshuman.khandual@arm.com> <1626229291-6569-7-git-send-email-anshuman.khandual@arm.com> <9f0d9925-3694-3fae-0d09-00adbecd1878@arm.com> Message-ID: <416867c1-f2aa-bd17-c8a3-9e7d8ceb015b@arm.com> Date: Fri, 16 Jul 2021 20:07:08 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Authentication-Results: imf17.hostedemail.com; dkim=none; dmarc=pass (policy=none) header.from=arm.com; spf=pass (imf17.hostedemail.com: domain of anshuman.khandual@arm.com designates 217.140.110.172 as permitted sender) smtp.mailfrom=anshuman.khandual@arm.com X-Rspamd-Server: rspam03 X-Rspamd-Queue-Id: 7B2F3F002C9B X-Stat-Signature: uds37my6eo67pmq1fxpmsoouidu3tzrd X-HE-Tag: 1626446185-771881 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On 7/16/21 3:32 PM, Steven Price wrote: > On 16/07/2021 08:20, Anshuman Khandual wrote: >> >> >> On 7/14/21 9:08 PM, Steven Price wrote: >>> On 14/07/2021 03:21, Anshuman Khandual wrote: >>>> FEAT_LPA2 requires different PTE representation formats for both 4K and 16K >>>> page size config. This adds FEAT_LPA2 specific new PTE encodings as per ARM >>>> ARM (0487G.A) which updates [pte|phys]_to_[phys|pte](). The updated helpers >>>> would be used when FEAT_LPA2 gets enabled via CONFIG_ARM64_PA_BITS_52 on 4K >>>> and 16K page size. Although TTBR encoding and phys_to_ttbr() helper remains >>>> the same as FEAT_LPA for FEAT_LPA2 as well. It updates 'phys_to_pte' helper >>>> to accept a temporary variable and changes impacted call sites. >>>> >>>> Signed-off-by: Anshuman Khandual >>>> --- >>>> arch/arm64/include/asm/assembler.h | 23 +++++++++++++++++++---- >>>> arch/arm64/include/asm/pgtable-hwdef.h | 4 ++++ >>>> arch/arm64/include/asm/pgtable.h | 4 ++++ >>>> arch/arm64/kernel/head.S | 25 +++++++++++++------------ >>>> 4 files changed, 40 insertions(+), 16 deletions(-) >>>> >>>> diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h >>>> index fedc202..0492543 100644 >>>> --- a/arch/arm64/include/asm/assembler.h >>>> +++ b/arch/arm64/include/asm/assembler.h >>>> @@ -606,7 +606,7 @@ alternative_endif >>>> #endif >>>> .endm >>>> >>>> - .macro phys_to_pte, pte, phys >>>> + .macro phys_to_pte, pte, phys, tmp >>>> #ifdef CONFIG_ARM64_PA_BITS_52_LPA >>>> /* >>>> * We assume \phys is 64K aligned and this is guaranteed by only >>>> @@ -614,6 +614,17 @@ alternative_endif >>>> */ >>>> orr \pte, \phys, \phys, lsr #36 >>>> and \pte, \pte, #PTE_ADDR_MASK >>>> +#elif defined(CONFIG_ARM64_PA_BITS_52_LPA2) >>>> + orr \pte, \phys, \phys, lsr #42 >>>> + >>>> + /* >>>> + * The 'tmp' is being used here to just prepare >>>> + * and hold PTE_ADDR_MASK which cannot be passed >>>> + * to the subsequent 'and' instruction. >>>> + */ >>>> + mov \tmp, #PTE_ADDR_LOW >>>> + orr \tmp, \tmp, #PTE_ADDR_HIGH >>>> + and \pte, \pte, \tmp >>> Rather than adding an extra temporary register (and the fallout of >>> various other macros needing an extra register), this can be done with >>> two AND instructions: >> >> I would really like to get rid of the 'tmp' variable here as >> well but did not figure out any method of accomplishing it. >> >>> >>> /* PTE_ADDR_MASK cannot be encoded as an immediate, so >>> * mask off all but two bits, followed by masking the >>> * extra two bits >>> */ >>> and \pte, \pte, #PTE_ADDR_MASK | (3 << 10) >>> and \pte, \pte, #~(3 << 10) >> >> Did this change as suggested >> >> --- a/arch/arm64/include/asm/assembler.h >> +++ b/arch/arm64/include/asm/assembler.h >> @@ -626,9 +626,8 @@ alternative_endif >> * and hold PTE_ADDR_MASK which cannot be passed >> * to the subsequent 'and' instruction. >> */ >> - mov \tmp, #PTE_ADDR_LOW >> - orr \tmp, \tmp, #PTE_ADDR_HIGH >> - and \pte, \pte, \tmp >> + and \pte, \pte, #PTE_ADDR_MASK | (0x3 << 10) >> + and \pte, \pte, #~(0x3 << 10) >> >> .Lskip_lpa2\@: >> mov \pte, \phys >> >> >> but still fails to build (tested on 16K) >> >> arch/arm64/kernel/head.S: Assembler messages: >> arch/arm64/kernel/head.S:377: Error: immediate out of range at operand 3 -- `and x6,x6,#((((1<<(50-14))-1)<<14)|(0x3<<8))|(0x3<<10)' >> arch/arm64/kernel/head.S:390: Error: immediate out of range at operand 3 -- `and x12,x12,#((((1<<(50-14))-1)<<14)|(0x3<<8))|(0x3<<10)' >> arch/arm64/kernel/head.S:390: Error: immediate out of range at operand 3 -- `and x12,x12,#((((1<<(50-14))-1)<<14)|(0x3<<8))|(0x3<<10)' >> arch/arm64/kernel/head.S:404: Error: immediate out of range at operand 3 -- `and x12,x12,#((((1<<(50-14))-1)<<14)|(0x3<<8))|(0x3<<10)' >> arch/arm64/kernel/head.S:404: Error: immediate out of range at operand 3 -- `and x12,x12,#((((1<<(50-14))-1)<<14)|(0x3<<8))|(0x3<<10)' >> > > Ah, I'd only tested this for 4k. 16k would require a different set of masks. > > So the bits we need to cover are those from just below PAGE_SHIFT to the > top of PTE_ADDR_HIGH (bit 10). So we can compute the mask for both 4k Okay. > and 16k with GENMASK(PAGE_SHIFT-1, 10): > > and \pte, \pte, #PTE_ADDR_MASK | GENMASK(PAGE_SHIFT - 1, 10) > and \pte, \pte, #~GENMASK(PAGE_SHIFT - 1, 10) > > This compiles (for both 4k and 16k) and the assembly looks correct, but > I've not done any other testing. Yeah it works, will do the change.