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From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Boris Ostrovsky <boris.ostrovsky@oracle.com>,
	"Kirill A. Shutemov" <kirill@shutemov.name>,
	"Zhang, Xiong Y" <xiong.y.zhang@intel.com>
Cc: linux-arch@vger.kernel.org, Juergen Gross <jgross@suse.com>,
	Andi Kleen <ak@linux.intel.com>, Arnd Bergmann <arnd@arndb.de>,
	linux-mm@kvack.org, x86@kernel.org, linux-kernel@vger.kernel.org,
	Andy Lutomirski <luto@amacapital.net>,
	Dave Hansen <dave.hansen@intel.com>,
	Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
	Andrew Morton <akpm@linux-foundation.org>,
	xen-devel <xen-devel@lists.xen.org>,
	Linus Torvalds <torvalds@linux-foundation.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Subject: Re: [Xen-devel] [PATCHv4 18/33] x86/xen: convert __xen_pgd_walk() and xen_cleanmfnmap() to support p4d
Date: Tue, 7 Mar 2017 18:26:05 +0000	[thread overview]
Message-ID: <47f06f4a-ef29-5a77-c48b-43a91a8c9579@citrix.com> (raw)
In-Reply-To: <8bd7d5b7-7a22-a0a2-8eff-e909a1c6783e@oracle.com>

On 07/03/17 18:18, Boris Ostrovsky wrote:
>>> Don't we need to pass vaddr down to all routines so that they select
>>> appropriate tables? You seem to always be choosing the first one.
>> IIUC, we clear whole page table subtree covered by one pgd entry.
>> So, no, there's no need to pass vaddr down. Just pointer to page table
>> entry is enough.
>>
>> But I know virtually nothing about Xen. Please re-check my reasoning.
> Yes, we effectively remove the whole page table for vaddr so I guess
> it's OK.
>
>> I would also appreciate help with getting x86 Xen code work with 5-level
>> paging enabled. For now I make CONFIG_XEN dependent on !CONFIG_X86_5LEVEL.
> Hmmm... that's a problem since this requires changes in the hypervisor
> and even if/when these changes are made older version of hypervisor
> still will not be able to run those guests.
>
> This affects only PV guests and there is a series under review that
> provides clean code separation with CONFIG_XEN_PV but because, for
> example, dom0 (Xen control domain) is PV this will significantly limit
> availability of dom0-capable kernels (because I assume distros will want
> to have CONFIG_X86_5LEVEL).

Wasn't the plan to be able to automatically detect 4 vs 5 level support,
and cope either way, so distros didn't have to ship two different builds
of Linux?

If so, all we need to do git things to compile sensibly, and have the PV
entry code in Linux configure the rest of the kernel appropriately.

(If not, please ignore me.)

~Andrew

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  reply	other threads:[~2017-03-07 18:26 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-06 13:53 [PATCHv4 00/33] 5-level paging Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 01/33] x86/cpufeature: Add 5-level paging detection Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 02/33] asm-generic: introduce 5level-fixup.h Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 03/33] asm-generic: introduce __ARCH_USE_5LEVEL_HACK Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 04/33] arch, mm: convert all architectures to use 5level-fixup.h Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 05/33] asm-generic: introduce <asm-generic/pgtable-nop4d.h> Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 06/33] mm: convert generic code to 5-level paging Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 07/33] mm: introduce __p4d_alloc() Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 08/33] x86: basic changes into headers for 5-level paging Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 09/33] x86: trivial portion of 5-level paging conversion Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 10/33] x86/gup: add 5-level paging support Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 11/33] x86/ident_map: " Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 12/33] x86/mm: add support of p4d_t in vmalloc_fault() Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 13/33] x86/power: support p4d_t in hibernate code Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 14/33] x86/kexec: support p4d_t Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 15/33] x86/efi: handle p4d in EFI pagetables Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 16/33] x86/mm/pat: handle additional page table Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 17/33] x86/kasan: prepare clear_pgds() to switch to <asm-generic/pgtable-nop4d.h> Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 18/33] x86/xen: convert __xen_pgd_walk() and xen_cleanmfnmap() to support p4d Kirill A. Shutemov
2017-03-06 20:48   ` Boris Ostrovsky
2017-03-07 13:00     ` Kirill A. Shutemov
2017-03-07 18:18       ` Boris Ostrovsky
2017-03-07 18:26         ` Andrew Cooper [this message]
2017-03-07 18:45           ` [Xen-devel] " Boris Ostrovsky
2017-03-06 13:53 ` [PATCHv4 19/33] x86: convert the rest of the code to support p4d_t Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 20/33] x86: detect 5-level paging support Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 21/33] x86/asm: remove __VIRTUAL_MASK_SHIFT==47 assert Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 22/33] x86/mm: define virtual memory map for 5-level paging Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 23/33] x86/paravirt: make paravirt code support " Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 24/33] x86/mm: basic defines/helpers for CONFIG_X86_5LEVEL Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 25/33] x86/dump_pagetables: support 5-level paging Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 26/33] x86/kasan: extend to " Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 27/33] x86/espfix: " Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 28/33] x86/mm: add support of additional page table level during early boot Kirill A. Shutemov
2017-03-06 20:05   ` Boris Ostrovsky
2017-03-06 20:23     ` Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 29/33] x86/mm: add sync_global_pgds() for configuration with 5-level paging Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 30/33] x86/mm: make kernel_physical_mapping_init() support " Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 31/33] x86/mm: add support for 5-level paging for KASLR Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 32/33] x86: enable 5-level paging support Kirill A. Shutemov
2017-03-06 13:53 ` [PATCHv4 33/33] x86/mm: allow to have userspace mappigs above 47-bits Kirill A. Shutemov
2017-03-06 18:27 ` [PATCHv4 00/33] 5-level paging Linus Torvalds
2017-03-06 18:42   ` Thomas Gleixner
2017-03-06 19:03     ` Linus Torvalds
2017-03-06 19:09       ` Kirill A. Shutemov
2017-03-06 19:35         ` Linus Torvalds
2017-03-07  0:41     ` Stephen Rothwell
2017-03-07  9:32       ` Thomas Gleixner

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