From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 100B2C388F7 for ; Tue, 10 Nov 2020 12:22:27 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 5A77E206B6 for ; Tue, 10 Nov 2020 12:22:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=agner.ch header.i=@agner.ch header.b="bbp/I2Ft" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5A77E206B6 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=agner.ch Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id 764386B005C; Tue, 10 Nov 2020 07:22:25 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 715A26B006C; Tue, 10 Nov 2020 07:22:25 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 6040F6B006E; Tue, 10 Nov 2020 07:22:25 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0224.hostedemail.com [216.40.44.224]) by kanga.kvack.org (Postfix) with ESMTP id 33D226B005C for ; Tue, 10 Nov 2020 07:22:25 -0500 (EST) Received: from smtpin02.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay04.hostedemail.com (Postfix) with ESMTP id C59DA1EE6 for ; Tue, 10 Nov 2020 12:22:24 +0000 (UTC) X-FDA: 77468421408.02.act39_0a11c4e272f5 Received: from filter.hostedemail.com (10.5.16.251.rfc1918.com [10.5.16.251]) by smtpin02.hostedemail.com (Postfix) with ESMTP id ABA0F10097AA0 for ; Tue, 10 Nov 2020 12:22:24 +0000 (UTC) X-HE-Tag: act39_0a11c4e272f5 X-Filterd-Recvd-Size: 6141 Received: from mail.kmu-office.ch (mail.kmu-office.ch [178.209.48.109]) by imf33.hostedemail.com (Postfix) with ESMTP for ; Tue, 10 Nov 2020 12:22:23 +0000 (UTC) Received: from webmail.kmu-office.ch (unknown [IPv6:2a02:418:6a02::a3]) by mail.kmu-office.ch (Postfix) with ESMTPSA id AF4A95C2D98; Tue, 10 Nov 2020 13:22:20 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=agner.ch; s=dkim; t=1605010940; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RsKAQhsjBAFRDGDj3c5k8MVs+xkOLwwQU+TEcjoUYn8=; b=bbp/I2FtCw6mOgT0qPJOd3lzI/1lpJiWfOcaEXzLWCwaI05gsT515QaI/aTSdOsajR8w9E ZGrP/D9lcA8UxuKm/CiMj5uvOLIv+wiW86w8q4BdBELTv50eEKJGRL/EL3HJKwKTyrG6HJ FPEKZ4Wg6uBj+0JGfRYgkY8wG5eSMSU= MIME-Version: 1.0 Date: Tue, 10 Nov 2020 13:22:20 +0100 From: Stefan Agner To: Arnd Bergmann Cc: Mike Rapoport , Minchan Kim , ngupta@vflare.org, Sergey Senozhatsky , Andrew Morton , sjenning@linux.vnet.ibm.com, gregkh , Arnd Bergmann , Linux-MM , linux-kernel@vger.kernel.org, linux@armlinux.org.uk Subject: Re: [PATCH] mm/zsmalloc: include sparsemem.h for MAX_PHYSMEM_BITS In-Reply-To: References: <20201108064659.GD301837@kernel.org> <7782fb694a6b0c500e8f32ecf895b2bf@agner.ch> <20201110095806.GH301837@kernel.org> User-Agent: Roundcube Webmail/1.4.9 Message-ID: <48fdc3631bc74dd77fea1a30085c8af9@agner.ch> X-Sender: stefan@agner.ch Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: [adding Russell King for ARM] On 2020-11-10 12:21, Arnd Bergmann wrote: > On Tue, Nov 10, 2020 at 10:58 AM Mike Rapoport wrote: >> > > >> > > asm/sparsemem.h is not available on some architectures. >> > > It's better to use linux/mmzone.h instead. > > Ah, I missed that, too. > >> > Hm, linux/mmzone.h only includes asm/sparsemem.h when CONFIG_SPARSEMEM >> > is enabled. However, on ARM at least I can have configurations without >> > CONFIG_SPARSEMEM and physical address extension on (e.g. >> > multi_v7_defconfig + CONFIG_LPAE + CONFIG_ZSMALLOC). >> > >> > While sparsemem seems to be a good idea with LPAE it really seems not >> > required (see also https://lore.kernel.org/patchwork/patch/567589/). >> > >> > There seem to be also other architectures which define MAX_PHYSMEM_BITS >> > only when SPARSEMEM is enabled, e.g. >> > arch/riscv/include/asm/sparsemem.h... >> > >> > Not sure how to get out of this.. Maybe make ZSMALLOC dependent on >> > SPARSEMEM? It feels a bit silly restricting ZSMALLOC selection only due >> > to a compile time define... >> >> I think we can define MAX_POSSIBLE_PHYSMEM_BITS in one of >> arch/arm/inclide/asm/pgtable-{2,3}level-*.h headers to values supported >> by !LPAE and LPAE. Hm I see mm/zsmalloc.c really only needs to know how many bits are potentially used to calculate how many bits it can use for object indexing. > > Good idea. I wonder what other architectures need the same though. > Here are some I found: > > $ git grep -l PHYS_ADDR_T_64BIT arch | grep Kconfig > arch/arc/Kconfig > arch/arm/mm/Kconfig > arch/mips/Kconfig > arch/powerpc/platforms/Kconfig.cputype > arch/x86/Kconfig > > arch/arc has a CONFIG_ARC_HAS_PAE40 option > arch/riscv has 34-bit addressing in rv32 mode > arch/mips has up to 40 bits with mips32r3 XPA, but I don't know what > supports that > > arch/powerpc has this: > config PHYS_64BIT > bool 'Large physical address support' if E500 || PPC_86xx > depends on (44x || E500 || PPC_86xx) && !PPC_83xx && !PPC_82xx > > Apparently all three (4xx, e500v2, mpc86xx/e600) do 36-bit physical > addressing, but each one has a different page table format. > > Microblaze has physical address extensions, but neither those nor > 64-bit mode have so far made it into the kernel. > > To be on the safe side, we could provoke a compile-time error > when CONFIG_PHYS_ADDR_T_64BIT is set on a 32-bit > architecture, but MAX_POSSIBLE_PHYSMEM_BITS is not set. > >> That's what x86 does: >> >> $ git grep -w MAX_POSSIBLE_PHYSMEM_BITS arch/ >> arch/x86/include/asm/pgtable-3level_types.h:#define MAX_POSSIBLE_PHYSMEM_BITS 36 > > Doesn't x86 also support a 40-bit addressing mode? I suppose > those machines that actually used it are long gone. > >> arch/x86/include/asm/pgtable_64_types.h:#define MAX_POSSIBLE_PHYSMEM_BITS 52 >> >> It seems that actual numbers would be 36 for !LPAE and 40 for LPAE, but >> I'm not sure about that. > > Close enough, yes. > > The 36-bit addressing is on !LPAE is only used for early static mappings, > so I think we can pretend it's always 32-bit. I checked the ARMv8 reference, > and it says that ARMv8-Aarch32 actually supports 40 bit physical addressing > both with non-LPAE superpages (short descriptor format) and LPAE (long > descriptor format), but Linux only does 36-bit addressing on superpages > as specified for ARMv6/ARMv7 short descriptors. Oh so, more than 4GB of memory can be supported by !LPAE systems via superpages? Wasn't aware of that. Since only ARM_LPAE selects CONFIG_PHYS_ADDR_T_64BIT it really is safe to assume 32 bits for non-LPAE systems. I guess that would mean adding a #define MAX_POSSIBLE_PHYSMEM_BITS 32 to arch/arm/include/asm/pgtable-2level.h and a MAX_POSSIBLE_PHYSMEM_BITS 40 in arch/arm/include/asm/pgtable-3level.h. Seems straight forward and would solve the problem I had. I can prepare a patch for ARM, not sure about the other architectures... -- Stefan