From: Nadav Amit <nadav.amit@gmail.com>
To: Andy Lutomirski <luto@kernel.org>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>,
Linux-MM <linux-mm@kvack.org>,
LKML <linux-kernel@vger.kernel.org>,
Andrea Arcangeli <aarcange@redhat.com>,
Andrew Morton <akpm@linux-foundation.org>,
Dave Hansen <dave.hansen@linux.intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Thomas Gleixner <tglx@linutronix.de>,
Will Deacon <will@kernel.org>, Yu Zhao <yuzhao@google.com>,
Nick Piggin <npiggin@gmail.com>, X86 ML <x86@kernel.org>
Subject: Re: [RFC 03/20] mm/mprotect: do not flush on permission promotion
Date: Sat, 30 Jan 2021 17:17:31 -0800 [thread overview]
Message-ID: <68D3C593-A88C-4100-90E9-E90F7733344F@gmail.com> (raw)
In-Reply-To: <CALCETrWxyMsD5zEoaFS-aVfkV=QiVWa7pCU_JE3AYDEEU8Hqvg@mail.gmail.com>
> On Jan 30, 2021, at 5:07 PM, Andy Lutomirski <luto@kernel.org> wrote:
>
> Adding Andrew Cooper, who has a distressingly extensive understanding
> of the x86 PTE magic.
>
> On Sat, Jan 30, 2021 at 4:16 PM Nadav Amit <nadav.amit@gmail.com> wrote:
>> From: Nadav Amit <namit@vmware.com>
>>
>> Currently, using mprotect() to unprotect a memory region or uffd to
>> unprotect a memory region causes a TLB flush. At least on x86, as
>> protection is promoted, no TLB flush is needed.
>>
>> Add an arch-specific pte_may_need_flush() which tells whether a TLB
>> flush is needed based on the old PTE and the new one. Implement an x86
>> pte_may_need_flush().
>>
>> For x86, besides the simple logic that PTE protection promotion or
>> changes of software bits does require a flush, also add logic that
>> considers the dirty-bit. If the dirty-bit is clear and write-protect is
>> set, no TLB flush is needed, as x86 updates the dirty-bit atomically
>> on write, and if the bit is clear, the PTE is reread.
>>
>> Signed-off-by: Nadav Amit <namit@vmware.com>
>> Cc: Andrea Arcangeli <aarcange@redhat.com>
>> Cc: Andrew Morton <akpm@linux-foundation.org>
>> Cc: Andy Lutomirski <luto@kernel.org>
>> Cc: Dave Hansen <dave.hansen@linux.intel.com>
>> Cc: Peter Zijlstra <peterz@infradead.org>
>> Cc: Thomas Gleixner <tglx@linutronix.de>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Yu Zhao <yuzhao@google.com>
>> Cc: Nick Piggin <npiggin@gmail.com>
>> Cc: x86@kernel.org
>> ---
>> arch/x86/include/asm/tlbflush.h | 44 +++++++++++++++++++++++++++++++++
>> include/asm-generic/tlb.h | 4 +++
>> mm/mprotect.c | 3 ++-
>> 3 files changed, 50 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
>> index 8c87a2e0b660..a617dc0a9b06 100644
>> --- a/arch/x86/include/asm/tlbflush.h
>> +++ b/arch/x86/include/asm/tlbflush.h
>> @@ -255,6 +255,50 @@ static inline void arch_tlbbatch_add_mm(struct arch_tlbflush_unmap_batch *batch,
>>
>> extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch);
>>
>> +static inline bool pte_may_need_flush(pte_t oldpte, pte_t newpte)
>> +{
>> + const pteval_t ignore_mask = _PAGE_SOFTW1 | _PAGE_SOFTW2 |
>> + _PAGE_SOFTW3 | _PAGE_ACCESSED;
>
> Why is accessed ignored? Surely clearing the accessed bit needs a
> flush if the old PTE is present.
I am just following the current scheme in the kernel (x86):
int ptep_clear_flush_young(struct vm_area_struct *vma,
unsigned long address, pte_t *ptep)
{
/*
* On x86 CPUs, clearing the accessed bit without a TLB flush
* doesn't cause data corruption. [ It could cause incorrect
* page aging and the (mistaken) reclaim of hot pages, but the
* chance of that should be relatively low. ]
*
* So as a performance optimization don't flush the TLB when
* clearing the accessed bit, it will eventually be flushed by
* a context switch or a VM operation anyway. [ In the rare
* event of it not getting flushed for a long time the delay
* shouldn't really matter because there's no real memory
* pressure for swapout to react to. ]
*/
return ptep_test_and_clear_young(vma, address, ptep);
}
>
>> + const pteval_t enable_mask = _PAGE_RW | _PAGE_DIRTY | _PAGE_GLOBAL;
>> + pteval_t oldval = pte_val(oldpte);
>> + pteval_t newval = pte_val(newpte);
>> + pteval_t diff = oldval ^ newval;
>> + pteval_t disable_mask = 0;
>> +
>> + if (IS_ENABLED(CONFIG_X86_64) || IS_ENABLED(CONFIG_X86_PAE))
>> + disable_mask = _PAGE_NX;
>> +
>> + /* new is non-present: need only if old is present */
>> + if (pte_none(newpte))
>> + return !pte_none(oldpte);
>> +
>> + /*
>> + * If, excluding the ignored bits, only RW and dirty are cleared and the
>> + * old PTE does not have the dirty-bit set, we can avoid a flush. This
>> + * is possible since x86 architecture set the dirty bit atomically while
>
> s/set/sets/
>
>> + * it caches the PTE in the TLB.
>> + *
>> + * The condition considers any change to RW and dirty as not requiring
>> + * flush if the old PTE is not dirty or not writable for simplification
>> + * of the code and to consider (unlikely) cases of changing dirty-bit of
>> + * write-protected PTE.
>> + */
>> + if (!(diff & ~(_PAGE_RW | _PAGE_DIRTY | ignore_mask)) &&
>> + (!(pte_dirty(oldpte) || !pte_write(oldpte))))
>> + return false;
>
> This logic seems confusing to me. Is your goal to say that, if the
> old PTE was clean and writable and the new PTE is write-protected,
> then no flush is needed?
Yes.
> If so, I would believe you're right, but I'm
> not convinced you've actually implemented this. Also, there may be
> other things going on that need flushing, e.g. a change of the address
> or an accessed bit or NX change.
The first part (diff & ~(_PAGE_RW | _PAGE_DIRTY | ignore_mask) is supposed
to capture changes of address, NX-bit, etc.
The second part is indeed wrong. It should have been:
(!pte_dirty(oldpte) || !pte_write(oldpte))
>
> Also, CET makes this extra bizarre.
I saw something about the not-writeable-and-dirty considered differently. I
need to have a look, but I am not sure it affects anything.
next prev parent reply other threads:[~2021-01-31 1:17 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-31 0:11 [RFC 00/20] TLB batching consolidation and enhancements Nadav Amit
2021-01-31 0:11 ` [RFC 01/20] mm/tlb: fix fullmm semantics Nadav Amit
2021-01-31 1:02 ` Andy Lutomirski
2021-01-31 1:19 ` Nadav Amit
2021-01-31 2:57 ` Andy Lutomirski
2021-02-01 7:30 ` Nadav Amit
2021-02-01 11:36 ` Peter Zijlstra
2021-02-02 9:32 ` Nadav Amit
2021-02-02 11:00 ` Peter Zijlstra
2021-02-02 21:35 ` Nadav Amit
2021-02-03 9:44 ` Will Deacon
2021-02-04 3:20 ` Nadav Amit
2021-01-31 0:11 ` [RFC 02/20] mm/mprotect: use mmu_gather Nadav Amit
2021-01-31 0:11 ` [RFC 03/20] mm/mprotect: do not flush on permission promotion Nadav Amit
2021-01-31 1:07 ` Andy Lutomirski
2021-01-31 1:17 ` Nadav Amit [this message]
2021-01-31 2:59 ` Andy Lutomirski
[not found] ` <7a6de15a-a570-31f2-14d6-a8010296e694@citrix.com>
2021-02-01 5:58 ` Nadav Amit
2021-02-01 15:38 ` Andrew Cooper
2021-01-31 0:11 ` [RFC 04/20] mm/mapping_dirty_helpers: use mmu_gather Nadav Amit
2021-01-31 0:11 ` [RFC 05/20] mm/tlb: move BATCHED_UNMAP_TLB_FLUSH to tlb.h Nadav Amit
2021-01-31 0:11 ` [RFC 06/20] fs/task_mmu: use mmu_gather interface of clear-soft-dirty Nadav Amit
2021-01-31 0:11 ` [RFC 07/20] mm: move x86 tlb_gen to generic code Nadav Amit
2021-01-31 18:26 ` Andy Lutomirski
2021-01-31 0:11 ` [RFC 08/20] mm: store completed TLB generation Nadav Amit
2021-01-31 20:32 ` Andy Lutomirski
2021-02-01 7:28 ` Nadav Amit
2021-02-01 16:53 ` Andy Lutomirski
2021-02-01 11:52 ` Peter Zijlstra
2021-01-31 0:11 ` [RFC 09/20] mm: create pte/pmd_tlb_flush_pending() Nadav Amit
2021-01-31 0:11 ` [RFC 10/20] mm: add pte_to_page() Nadav Amit
2021-01-31 0:11 ` [RFC 11/20] mm/tlb: remove arch-specific tlb_start/end_vma() Nadav Amit
2021-02-01 12:09 ` Peter Zijlstra
2021-02-02 6:41 ` Nicholas Piggin
2021-02-02 7:20 ` Nadav Amit
2021-02-02 9:31 ` Peter Zijlstra
2021-02-02 9:54 ` Nadav Amit
2021-02-02 11:04 ` Peter Zijlstra
2021-01-31 0:11 ` [RFC 12/20] mm/tlb: save the VMA that is flushed during tlb_start_vma() Nadav Amit
2021-02-01 12:28 ` Peter Zijlstra
2021-01-31 0:11 ` [RFC 13/20] mm/tlb: introduce tlb_start_ptes() and tlb_end_ptes() Nadav Amit
2021-01-31 9:57 ` Damian Tometzki
2021-01-31 10:07 ` Damian Tometzki
2021-02-01 7:29 ` Nadav Amit
2021-02-01 13:19 ` Peter Zijlstra
2021-02-01 23:00 ` Nadav Amit
2021-01-31 0:11 ` [RFC 14/20] mm: move inc/dec_tlb_flush_pending() to mmu_gather.c Nadav Amit
2021-01-31 0:11 ` [RFC 15/20] mm: detect deferred TLB flushes in vma granularity Nadav Amit
2021-02-01 22:04 ` Nadav Amit
2021-02-02 0:14 ` Andy Lutomirski
2021-02-02 20:51 ` Nadav Amit
2021-02-04 4:35 ` Andy Lutomirski
2021-01-31 0:11 ` [RFC 16/20] mm/tlb: per-page table generation tracking Nadav Amit
2021-01-31 0:11 ` [RFC 17/20] mm/tlb: updated completed deferred TLB flush conditionally Nadav Amit
2021-01-31 0:11 ` [RFC 18/20] mm: make mm_cpumask() volatile Nadav Amit
2021-01-31 0:11 ` [RFC 19/20] lib/cpumask: introduce cpumask_atomic_or() Nadav Amit
2021-01-31 0:11 ` [RFC 20/20] mm/rmap: avoid potential races Nadav Amit
2021-08-23 8:05 ` Huang, Ying
2021-08-23 15:50 ` Nadav Amit
2021-08-24 0:36 ` Huang, Ying
2021-01-31 0:39 ` [RFC 00/20] TLB batching consolidation and enhancements Andy Lutomirski
2021-01-31 1:08 ` Nadav Amit
2021-01-31 3:30 ` Nicholas Piggin
2021-01-31 7:57 ` Nadav Amit
2021-01-31 8:14 ` Nadav Amit
2021-02-01 12:44 ` Peter Zijlstra
2021-02-02 7:14 ` Nicholas Piggin
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