From: Zhenyu Ye <yezhenyu2@huawei.com>
To: <peterz@infradead.org>, <mark.rutland@arm.com>, <will@kernel.org>,
<catalin.marinas@arm.com>, <aneesh.kumar@linux.ibm.com>,
<akpm@linux-foundation.org>, <npiggin@gmail.com>, <arnd@arndb.de>,
<rostedt@goodmis.org>, <maz@kernel.org>, <suzuki.poulose@arm.com>,
<tglx@linutronix.de>, <yuzhao@google.com>, <Dave.Martin@arm.com>,
<steven.price@arm.com>, <broonie@kernel.org>,
<guohanjun@huawei.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-arch@vger.kernel.org>,
<linux-mm@kvack.org>, <arm@kernel.org>, <xiexiangyou@huawei.com>,
<prime.zeng@hisilicon.com>, <zhangshaokun@hisilicon.com>,
<kuhn.chenqun@huawei.com>
Subject: Re: [PATCH v2 0/6] arm64: tlb: add support for TTL feature
Date: Mon, 11 May 2020 20:41:24 +0800 [thread overview]
Message-ID: <6c59eae9-3a77-ef18-fac4-aa21e97fd1f0@huawei.com> (raw)
In-Reply-To: <20200423135656.2712-1-yezhenyu2@huawei.com>
Hi all,
How is this going about this patch series? Does anyone have any
suggestions?
Thanks,
Zhenyu
On 2020/4/23 21:56, Zhenyu Ye wrote:
> In order to reduce the cost of TLB invalidation, ARMv8.4 provides
> the TTL field in TLBI instruction. The TTL field indicates the
> level of page table walk holding the leaf entry for the address
> being invalidated. This series provide support for this feature.
>
> When ARMv8.4-TTL is implemented, the operand for TLBIs looks like
> below:
>
> * +----------+-------+----------------------+
> * | ASID | TTL | BADDR |
> * +----------+-------+----------------------+
> * |63 48|47 44|43 0|
>
>
> This version updates some codes implementation according to Peter's
> suggestion, and adds some commit msg.
>
> See patches for details, Thanks.
>
>
> --
> ChangeList:
> v2:
> rebase series on Linux 5.7-rc1 and simplify the code implementation.
>
> v1:
> add support for TTL feature in arm64.
>
> Marc Zyngier (2):
> arm64: Detect the ARMv8.4 TTL feature
> arm64: Add level-hinted TLB invalidation helper
>
> Peter Zijlstra (Intel) (1):
> tlb: mmu_gather: add tlb_flush_*_range APIs
>
> Zhenyu Ye (3):
> arm64: Add tlbi_user_level TLB invalidation helper
> mm: tlb: Provide flush_*_tlb_range wrappers
> arm64: tlb: Set the TTL field in flush_tlb_range
>
> arch/arm64/include/asm/cpucaps.h | 3 +-
> arch/arm64/include/asm/sysreg.h | 1 +
> arch/arm64/include/asm/tlb.h | 29 +++++++++++++++-
> arch/arm64/include/asm/tlbflush.h | 54 +++++++++++++++++++++++++-----
> arch/arm64/kernel/cpufeature.c | 11 +++++++
> include/asm-generic/pgtable.h | 12 +++++--
> include/asm-generic/tlb.h | 55 ++++++++++++++++++++++---------
> mm/pgtable-generic.c | 22 +++++++++++++
> 8 files changed, 160 insertions(+), 27 deletions(-)
>
prev parent reply other threads:[~2020-05-11 12:41 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-23 13:56 [PATCH v2 0/6] arm64: tlb: add support for TTL feature Zhenyu Ye
2020-04-23 13:56 ` [PATCH v2 1/6] arm64: Detect the ARMv8.4 " Zhenyu Ye
2020-05-22 15:50 ` Catalin Marinas
2020-04-23 13:56 ` [PATCH v2 2/6] arm64: Add level-hinted TLB invalidation helper Zhenyu Ye
2020-05-22 15:50 ` Catalin Marinas
2020-05-25 6:54 ` Zhenyu Ye
2020-04-23 13:56 ` [PATCH v2 3/6] arm64: Add tlbi_user_level " Zhenyu Ye
2020-05-22 15:49 ` Catalin Marinas
2020-05-25 6:57 ` Zhenyu Ye
2020-04-23 13:56 ` [PATCH v2 4/6] tlb: mmu_gather: add tlb_flush_*_range APIs Zhenyu Ye
2020-05-22 15:50 ` Catalin Marinas
2020-04-23 13:56 ` [PATCH v2 5/6] mm: tlb: Provide flush_*_tlb_range wrappers Zhenyu Ye
2020-05-22 15:42 ` Catalin Marinas
2020-05-25 7:19 ` Zhenyu Ye
2020-05-26 14:52 ` Catalin Marinas
2020-05-30 10:24 ` Zhenyu Ye
2020-06-01 11:56 ` Catalin Marinas
2020-06-01 13:36 ` Zhenyu Ye
2020-04-23 13:56 ` [PATCH v2 6/6] arm64: tlb: Set the TTL field in flush_tlb_range Zhenyu Ye
2020-05-26 14:56 ` Catalin Marinas
2020-05-11 12:41 ` Zhenyu Ye [this message]
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