From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D241C32771 for ; Wed, 28 Sep 2022 04:54:12 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 9C8238E011E; Wed, 28 Sep 2022 00:54:11 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 978FD8E00C1; Wed, 28 Sep 2022 00:54:11 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 8409E8E011E; Wed, 28 Sep 2022 00:54:11 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0010.hostedemail.com [216.40.44.10]) by kanga.kvack.org (Postfix) with ESMTP id 7101D8E00C1 for ; Wed, 28 Sep 2022 00:54:11 -0400 (EDT) Received: from smtpin09.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay08.hostedemail.com (Postfix) with ESMTP id 2B25B14098F for ; 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27 Sep 2022 21:54:07 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10483"; a="572895866" X-IronPort-AV: E=Sophos;i="5.93,351,1654585200"; d="scan'208";a="572895866" Received: from yhuang6-desk2.sh.intel.com (HELO yhuang6-desk2.ccr.corp.intel.com) ([10.238.208.55]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Sep 2022 21:54:04 -0700 From: "Huang, Ying" To: haoxin Cc: , , Andrew Morton , Zi Yan , Yang Shi , Baolin Wang , "Oscar Salvador" , Matthew Wilcox , , , <21cnbao@gmail.com> Subject: Re: [RFC 0/6] migrate_pages(): batch TLB flushing References: <20220921060616.73086-1-ying.huang@intel.com> <393d6318-aa38-01ed-6ad8-f9eac89bf0fc@linux.alibaba.com> <874jws2r6o.fsf@yhuang6-desk2.ccr.corp.intel.com> <02e9da8a-39af-f6bd-b7f3-c60b3f2a59fb@linux.alibaba.com> Date: Wed, 28 Sep 2022 12:53:18 +0800 In-Reply-To: <02e9da8a-39af-f6bd-b7f3-c60b3f2a59fb@linux.alibaba.com> (haoxin's message of "Wed, 28 Sep 2022 11:33:13 +0800") Message-ID: <87zgek14n5.fsf@yhuang6-desk2.ccr.corp.intel.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=ascii ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1664340850; a=rsa-sha256; cv=none; b=L7Idww376CNXGltxWaGVrjA6ZhMjPuFgONqbvOakyaJEfR63Pesxwj5bd3xAWYVQw3oOFE 17+/u3fdUZSuT6N3ei1hDV2sg4OFgaCNJ6eo6sg1+COqBkioJitTCxbIDO7Gp3TTIDUSll k0VpjeKp3HoT+RBJpsmt5BKlThL6s9A= ARC-Authentication-Results: i=1; imf24.hostedemail.com; dkim=none ("invalid DKIM record") header.d=intel.com header.s=Intel header.b=TKHJWqA5; spf=pass (imf24.hostedemail.com: domain of ying.huang@intel.com designates 192.55.52.151 as permitted sender) smtp.mailfrom=ying.huang@intel.com; dmarc=pass (policy=none) header.from=intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1664340850; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=byv+BiuLfHLK6DqwMRhrit91CvpurBrsoZrIjUttygw=; b=rPN/zQk8XARxUdn2ZCuSQ+JQa+gmRsX2+3/X5uu5V/SIyVK4q3OUQxr4kMjDPlqYzZjghC FjA4UHtzsZldagTCGOmj/D1QjVaqFKJ/4rHV5d3i+EEpiMG0KareqCl9f5E4U6DGv5ciAM WhTxCA/XYlF0BAHq4vrcAq66rBQmfPQ= X-Rspam-User: Authentication-Results: imf24.hostedemail.com; dkim=none ("invalid DKIM record") header.d=intel.com header.s=Intel header.b=TKHJWqA5; spf=pass (imf24.hostedemail.com: domain of ying.huang@intel.com designates 192.55.52.151 as permitted sender) smtp.mailfrom=ying.huang@intel.com; dmarc=pass (policy=none) header.from=intel.com X-Rspamd-Queue-Id: 66A65180007 X-Rspamd-Server: rspam03 X-Stat-Signature: 7raec9k9hgaw3inwfwppmcq4q3ocihm5 X-HE-Tag: 1664340849-120759 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: haoxin writes: > ( 2022/9/28 H10:01, Huang, Ying S: >> haoxin writes: >> >>> Hi, Huang >>> >>> ( 2022/9/21 H2:06, Huang Ying S: >>>> From: "Huang, Ying" >>>> >>>> Now, migrate_pages() migrate pages one by one, like the fake code as >>>> follows, >>>> >>>> for each page >>>> unmap >>>> flush TLB >>>> copy >>>> restore map >>>> >>>> If multiple pages are passed to migrate_pages(), there are >>>> opportunities to batch the TLB flushing and copying. That is, we can >>>> change the code to something as follows, >>>> >>>> for each page >>>> unmap >>>> for each page >>>> flush TLB >>>> for each page >>>> copy >>>> for each page >>>> restore map >>>> >>>> The total number of TLB flushing IPI can be reduced considerably. And >>>> we may use some hardware accelerator such as DSA to accelerate the >>>> page copying. >>>> >>>> So in this patch, we refactor the migrate_pages() implementation and >>>> implement the TLB flushing batching. Base on this, hardware >>>> accelerated page copying can be implemented. >>>> >>>> If too many pages are passed to migrate_pages(), in the naive batched >>>> implementation, we may unmap too many pages at the same time. The >>>> possibility for a task to wait for the migrated pages to be mapped >>>> again increases. So the latency may be hurt. To deal with this >>>> issue, the max number of pages be unmapped in batch is restricted to >>>> no more than HPAGE_PMD_NR. That is, the influence is at the same >>>> level of THP migration. >>>> >>>> We use the following test to measure the performance impact of the >>>> patchset, >>>> >>>> On a 2-socket Intel server, >>>> >>>> - Run pmbench memory accessing benchmark >>>> >>>> - Run `migratepages` to migrate pages of pmbench between node 0 and >>>> node 1 back and forth. >>>> >>> As the pmbench can not run on arm64 machine, so i use lmbench instead. >>> I test case like this: (i am not sure whether it is reasonable, but it seems worked) >>> ./bw_mem -N10000 10000m rd & >>> time migratepages pid node0 node1 >>> >>> o/patch w/patch >>> real 0m0.035s real 0m0.024s >>> user 0m0.000s user 0m0.000s >>> sys 0m0.035s sys 0m0.024s >>> >>> the migratepages time is reduced above 32%. >>> >>> But there has a problem, i see the batch flush is called by >>> migrate_pages_batch >>> try_to_unmap_flush >>> arch_tlbbatch_flush(&tlb_ubc->arch); // there batch flush really work. >>> >>> But in arm64, the arch_tlbbatch_flush are not supported, becasue it not support CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH yet. >>> >>> So, the tlb batch flush means no any flush is did, it is a empty func. >> Yes. And should_defer_flush() will always return false too. That is, >> the TLB will still be flushed, but will not be batched. > Oh, yes, i ignore this, thank you. >> >>> Maybe this patch can help solve this problem. >>> https://lore.kernel.org/linux-arm-kernel/20220921084302.43631-1-yangyicong@huawei.com/T/ >> Yes. This will bring TLB flush batching to ARM64. > Next time, i will combine with this patch, and do some test again, > do you have any suggestion about benchmark ? I think your benchmark should be OK. If multiple threads are used, the effect of patchset will be better. Best Regards, Huang, Ying