From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C17EBC388F9 for ; Wed, 11 Nov 2020 10:57:23 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id EF2802067D for ; Wed, 11 Nov 2020 10:57:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="zasY+T96" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EF2802067D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id 1496B6B0036; Wed, 11 Nov 2020 05:57:22 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 0D3E96B005D; Wed, 11 Nov 2020 05:57:22 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id EDC3E6B0068; Wed, 11 Nov 2020 05:57:21 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0066.hostedemail.com [216.40.44.66]) by kanga.kvack.org (Postfix) with ESMTP id BE5DF6B0036 for ; Wed, 11 Nov 2020 05:57:21 -0500 (EST) Received: from smtpin01.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay02.hostedemail.com (Postfix) with ESMTP id 6A7B8362B for ; Wed, 11 Nov 2020 10:57:21 +0000 (UTC) X-FDA: 77471835882.01.cloud03_0a0926c272fd Received: from filter.hostedemail.com (10.5.16.251.rfc1918.com [10.5.16.251]) by smtpin01.hostedemail.com (Postfix) with ESMTP id 4635510049A7A for ; Wed, 11 Nov 2020 10:57:21 +0000 (UTC) X-HE-Tag: cloud03_0a0926c272fd X-Filterd-Recvd-Size: 5039 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by imf32.hostedemail.com (Postfix) with ESMTP for ; Wed, 11 Nov 2020 10:57:20 +0000 (UTC) Received: from mail-oi1-f176.google.com (mail-oi1-f176.google.com [209.85.167.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 557172076E for ; Wed, 11 Nov 2020 10:57:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1605092239; bh=3cUrzEperZmJZPiBR0OisMLBYKRAFSIs72FijGKrXHk=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=zasY+T96Loq7v5mhXhs9smgNUamcpczR1ufJ3IAspaK+KJ1Wl5CSZAktxY5Sjfzre sb1llTAyRRE2cKsYVbFMFlsdH1JPFtjJkKUV371vveNYJuyWmbKp+rna+6ukD4Vgqj Tsg0yUZmlb/jdvH/CzsEbV4Td/VxWvKCMfD9i87k= Received: by mail-oi1-f176.google.com with SMTP id d9so1723782oib.3 for ; Wed, 11 Nov 2020 02:57:19 -0800 (PST) X-Gm-Message-State: AOAM532rcg86eHMLd19IdtwcpwER/XZINEREDAlzHlU/8429eNe3+JY0 Ews4fLohibALa/La4751yL0yNOZWdcCRDOSLIcg= X-Google-Smtp-Source: ABdhPJwO+gAy08wl+Li6qJXH9ISAmoM1KXb5s2HvOM4ZMAlkwL/wMgtFk6KMi/gnjXIIehnz5+mv25yP1hG199ZhGZs= X-Received: by 2002:aca:e0d7:: with SMTP id x206mr1833471oig.67.1605092238510; Wed, 11 Nov 2020 02:57:18 -0800 (PST) MIME-Version: 1.0 References: <20201108064659.GD301837@kernel.org> <7782fb694a6b0c500e8f32ecf895b2bf@agner.ch> <20201110095806.GH301837@kernel.org> <20201110162155.GA4758@kernel.org> <20201111102654.GF4758@kernel.org> In-Reply-To: <20201111102654.GF4758@kernel.org> From: Arnd Bergmann Date: Wed, 11 Nov 2020 11:57:02 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] mm/zsmalloc: include sparsemem.h for MAX_PHYSMEM_BITS To: Mike Rapoport Cc: Stefan Agner , Minchan Kim , ngupta@vflare.org, Sergey Senozhatsky , Andrew Morton , sjenning@linux.vnet.ibm.com, gregkh , Arnd Bergmann , Linux-MM , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Wed, Nov 11, 2020 at 11:26 AM Mike Rapoport wrote: > > On Wed, Nov 11, 2020 at 10:33:29AM +0100, Arnd Bergmann wrote: > > On Tue, Nov 10, 2020 at 5:21 PM Mike Rapoport wrote: > > > On Tue, Nov 10, 2020 at 12:21:11PM +0100, Arnd Bergmann wrote: > > > > > > > > To be on the safe side, we could provoke a compile-time error > > > > when CONFIG_PHYS_ADDR_T_64BIT is set on a 32-bit > > > > architecture, but MAX_POSSIBLE_PHYSMEM_BITS is not set. > > > > > > Maybe compile time warning and a runtime error in zs_init() if 32 bit > > > machine has memory above 4G? > > > > If the fix is as easy as adding a single line in a header, I think a > > compile-time > > error makes it easier, no need to wait for someone to boot a broken > > system before fixing it. > > Not sure it would be as easy as adding a single line in a header for > MIPS with it's diversity. I looked up the architecture, and found: - The pre-MIPS32r1 cores only support 32-bit addressing - octeon selects PHYS_ADDR_T_64BIT but no longer supports 32-bit kernels - Alchemy and netlogic (XLR, XLP) have 36-bit addressing - CONFIG_XPA implies 40-bit addressing We should run it by the MIPS maintainers, but I think this patch is sufficient: --- a/arch/mips/include/asm/pgtable-32.h +++ b/arch/mips/include/asm/pgtable-32.h @@ -154,6 +154,7 @@ static inline void pmd_clear(pmd_t *pmdp) #if defined(CONFIG_XPA) +#define MAX_POSSIBLE_PHYSMEM_BITS 40 #define pte_pfn(x) (((unsigned long)((x).pte_high >> _PFN_SHIFT)) | (unsigned long)((x).pte_low << _PAGE_PRESENT_SHIFT)) static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) @@ -169,6 +170,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot) #elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) +#define MAX_POSSIBLE_PHYSMEM_BITS 35 #define pte_pfn(x) ((unsigned long)((x).pte_high >> 6)) static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) @@ -183,6 +185,7 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) #else +#define MAX_POSSIBLE_PHYSMEM_BITS 32 #ifdef CONFIG_CPU_VR41XX #define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2))) #define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot)) Arnd