From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lb0-f176.google.com (mail-lb0-f176.google.com [209.85.217.176]) by kanga.kvack.org (Postfix) with ESMTP id 9B5806B0038 for ; Mon, 1 Jun 2015 13:11:15 -0400 (EDT) Received: by lbcue7 with SMTP id ue7so88786568lbc.0 for ; Mon, 01 Jun 2015 10:11:14 -0700 (PDT) Received: from mail-lb0-f181.google.com (mail-lb0-f181.google.com. [209.85.217.181]) by mx.google.com with ESMTPS id kh8si12808693lbc.46.2015.06.01.10.11.13 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 01 Jun 2015 10:11:13 -0700 (PDT) Received: by lbcue7 with SMTP id ue7so88786012lbc.0 for ; Mon, 01 Jun 2015 10:11:13 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <20150601085821.GA15014@gmail.com> References: <1432739944-22633-1-git-send-email-toshi.kani@hp.com> <1432739944-22633-13-git-send-email-toshi.kani@hp.com> <20150529091129.GC31435@pd.tnic> <1432911782.23540.55.camel@misato.fc.hp.com> <94D0CD8314A33A4D9D801C0FE68B40295A92F392@G9W0745.americas.hpqcorp.net> <20150601085821.GA15014@gmail.com> From: Andy Lutomirski Date: Mon, 1 Jun 2015 10:10:52 -0700 Message-ID: Subject: Re: [PATCH v10 12/12] drivers/block/pmem: Map NVDIMM with ioremap_wt() Content-Type: text/plain; charset=UTF-8 Sender: owner-linux-mm@kvack.org List-ID: To: Ingo Molnar Cc: "Elliott, Robert (Server Storage)" , Dan Williams , "Kani, Toshimitsu" , Borislav Petkov , Ross Zwisler , "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , Andrew Morton , Arnd Bergmann , "linux-mm@kvack.org" , "linux-kernel@vger.kernel.org" , X86 ML , "linux-nvdimm@lists.01.org" , Juergen Gross , Stefan Bader , Henrique de Moraes Holschuh , Yigal Korman , Konrad Rzeszutek Wilk , Luis Rodriguez , Christoph Hellwig , Matthew Wilcox On Mon, Jun 1, 2015 at 1:58 AM, Ingo Molnar wrote: > > * Andy Lutomirski wrote: > >> You answered the wrong question. :) I understand the point of the non-temporal >> stores -- I don't understand the point of using non-temporal stores to *WB >> memory*. I think we should be okay with having the kernel mapping use WT >> instead. > > WB memory is write-through, but they are still fully cached for reads. > > So non-temporal instructions influence how the CPU will allocate (or not allocate) > WT cache lines. > I'm doing a terrible job of saying what I mean. Given that we're using non-temporal writes, the kernel code should work correctly and with similar performance regardless of whether the mapping is WB or WT. It would still be correct, if slower, with WC or UC, and, if we used explicit streaming reads, even that would matter less. I think this means that we are free to switch the kernel mapping between WB and WT as needed to improve DAX behavior. We could even plausibly do it at runtime. --Andy > Thanks, > > Ingo -- Andy Lutomirski AMA Capital Management, LLC -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org