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[198.145.29.99]) by mx.google.com with ESMTPS id d3si3841491pgc.299.2019.06.10.12.56.02 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Jun 2019 12:56:02 -0700 (PDT) Received-SPF: pass (google.com: domain of luto@kernel.org designates 198.145.29.99 as permitted sender) client-ip=198.145.29.99; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=uLzHkUDA; spf=pass (google.com: domain of luto@kernel.org designates 198.145.29.99 as permitted sender) smtp.mailfrom=luto@kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 22F6B21744 for ; Mon, 10 Jun 2019 19:56:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1560196562; bh=BSrEs7k4Eaj+qfKqbXB7x6RBjqYairyQB7xlNqEmonI=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=uLzHkUDAQ8jOsA8YXnkz0O3Qklab8tzkEtYYWwVgKRQkiQKzSqsdLapdzrorKdIKK n6Eo4HwM27qI73UXdMC+Vo7aJo27Dlu5OTlBwsHayFksgsHw2rZwNM92HHc08myrfM frywWd5NERvhfQ373QnY3PfJ7m2L8vxY6KRo3fOE= Received: by mail-wm1-f44.google.com with SMTP id 207so558448wma.1 for ; Mon, 10 Jun 2019 12:56:02 -0700 (PDT) X-Received: by 2002:a7b:cd84:: with SMTP id y4mr14984047wmj.79.1560196560570; Mon, 10 Jun 2019 12:56:00 -0700 (PDT) MIME-Version: 1.0 References: <20190606200926.4029-1-yu-cheng.yu@intel.com> <20190606200926.4029-4-yu-cheng.yu@intel.com> <20190607080832.GT3419@hirez.programming.kicks-ass.net> <20190607174336.GM3436@hirez.programming.kicks-ass.net> <34E0D316-552A-401C-ABAA-5584B5BC98C5@amacapital.net> <7e0b97bf1fbe6ff20653a8e4e147c6285cc5552d.camel@intel.com> <25281DB3-FCE4-40C2-BADB-B3B05C5F8DD3@amacapital.net> <3f19582d-78b1-5849-ffd0-53e8ca747c0d@intel.com> <5aa98999b1343f34828414b74261201886ec4591.camel@intel.com> <0665416d-9999-b394-df17-f2a5e1408130@intel.com> In-Reply-To: <0665416d-9999-b394-df17-f2a5e1408130@intel.com> From: Andy Lutomirski Date: Mon, 10 Jun 2019 12:55:48 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v7 03/14] x86/cet/ibt: Add IBT legacy code bitmap setup function To: Dave Hansen Cc: Yu-cheng Yu , Peter Zijlstra , X86 ML , "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , LKML , "open list:DOCUMENTATION" , Linux-MM , linux-arch , Linux API , Arnd Bergmann , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H.J. Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Randy Dunlap , "Ravi V. Shankar" , Vedvyas Shanbhogue , Dave Martin Content-Type: text/plain; charset="UTF-8" X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Mon, Jun 10, 2019 at 12:52 PM Dave Hansen wrote: > > On 6/10/19 12:38 PM, Yu-cheng Yu wrote: > >>> When an application starts, its highest stack address is determined. > >>> It uses that as the maximum the bitmap needs to cover. > >> Huh, I didn't think we ran code from the stack. ;) > >> > >> Especially given the way that we implemented the new 5-level-paging > >> address space, I don't think that expecting code to be below the stack > >> is a good universal expectation. > > Yes, you make a good point. However, allowing the application manage the bitmap > > is the most efficient and flexible. If the loader finds a legacy lib is beyond > > the bitmap can cover, it can deal with the problem by moving the lib to a lower > > address; or re-allocate the bitmap. > > How could the loader reallocate the bitmap and coordinate with other > users of the bitmap? > > > If the loader cannot allocate a big bitmap to cover all 5-level > > address space (the bitmap will be large), it can put all legacy lib's > > at lower address. We cannot do these easily in the kernel. > > This is actually an argument to do it in the kernel. The kernel can > always allocate the virtual space however it wants, no matter how large. > If we hide the bitmap behind a kernel API then we can put it at high > 5-level user addresses because we also don't have to worry about the > high bits confusing userspace. > That's a fairly compelling argument. The bitmap is one bit per page, right? So it's smaller than the address space by a factor of 8*2^12 == 2^15. This means that, if we ever get full 64-bit linear addresses reserved entirely for userspace (which could happen if my perennial request to Intel to split user and kernel addresses completely happens), then we'll need 2^48 bytes for the bitmap, which simply does not fit in the address space of a legacy application.