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[2a0a:51c0:0:12e:550::1]) by mx.google.com with ESMTPS id z13si32683858wrs.40.2019.07.24.06.57.39 for (version=TLS1_2 cipher=AES128-SHA bits=128/128); Wed, 24 Jul 2019 06:57:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of tglx@linutronix.de designates 2a0a:51c0:0:12e:550::1 as permitted sender) client-ip=2a0a:51c0:0:12e:550::1; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of tglx@linutronix.de designates 2a0a:51c0:0:12e:550::1 as permitted sender) smtp.mailfrom=tglx@linutronix.de Received: from pd9ef1cb8.dip0.t-ipconnect.de ([217.239.28.184] helo=nanos) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1hqHlu-0001CA-H9; Wed, 24 Jul 2019 15:57:34 +0200 Date: Wed, 24 Jul 2019 15:57:33 +0200 (CEST) From: Thomas Gleixner To: Steven Price cc: Mark Rutland , x86@kernel.org, Arnd Bergmann , Ard Biesheuvel , Peter Zijlstra , Catalin Marinas , Dave Hansen , linux-kernel@vger.kernel.org, linux-mm@kvack.org, =?ISO-8859-15?Q?J=E9r=F4me_Glisse?= , Ingo Molnar , Borislav Petkov , Andy Lutomirski , "H. Peter Anvin" , James Morse , Will Deacon , Andrew Morton , linux-arm-kernel@lists.infradead.org, "Liang, Kan" Subject: Re: [PATCH v9 00/21] Generic page walk and ptdump In-Reply-To: Message-ID: References: <20190722154210.42799-1-steven.price@arm.com> <20190723101639.GD8085@lakrids.cambridge.arm.com> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Wed, 24 Jul 2019, Steven Price wrote: > On 23/07/2019 11:16, Mark Rutland wrote: > > Are there any visible changes to the arm64 output? > > arm64 output shouldn't change. I've confirmed that "efi_page_tables" is > identical on a Juno before/after the change. "kernel_page_tables" > obviously will vary depending on the exact layout of memory, but the > format isn't changed. > > x86 output does change due to patch 14. In this case the change is > removing the lines from the output of the form... > > > 0xffffffff84800000-0xffffffffa0000000 440M pmd > > ...which are unpopulated areas of the memory map. Populated lines which > have attributes are unchanged. Having the hole size and the level in the dump is a very conveniant thing. Right now we have: 0xffffffffc0427000-0xffffffffc042b000 16K ro NX pte 0xffffffffc042b000-0xffffffffc042e000 12K RW NX pte 0xffffffffc042e000-0xffffffffc042f000 4K pte 0xffffffffc042f000-0xffffffffc0430000 4K ro x pte 0xffffffffc0430000-0xffffffffc0431000 4K ro NX pte 0xffffffffc0431000-0xffffffffc0433000 8K RW NX pte 0xffffffffc0433000-0xffffffffc0434000 4K pte 0xffffffffc0434000-0xffffffffc0436000 8K ro x pte 0xffffffffc0436000-0xffffffffc0438000 8K ro NX pte 0xffffffffc0438000-0xffffffffc043a000 8K RW NX pte 0xffffffffc043a000-0xffffffffc043f000 20K pte 0xffffffffc043f000-0xffffffffc0444000 20K ro x pte 0xffffffffc0444000-0xffffffffc0447000 12K ro NX pte 0xffffffffc0447000-0xffffffffc0449000 8K RW NX pte 0xffffffffc0449000-0xffffffffc044f000 24K pte 0xffffffffc044f000-0xffffffffc0450000 4K ro x pte 0xffffffffc0450000-0xffffffffc0451000 4K ro NX pte 0xffffffffc0451000-0xffffffffc0453000 8K RW NX pte 0xffffffffc0453000-0xffffffffc0458000 20K pte 0xffffffffc0458000-0xffffffffc0459000 4K ro x pte 0xffffffffc0459000-0xffffffffc045b000 8K ro NX pte with your change this becomes: 0xffffffffc0427000-0xffffffffc042b000 16K ro NX pte 0xffffffffc042b000-0xffffffffc042e000 12K RW NX pte 0xffffffffc042f000-0xffffffffc0430000 4K ro x pte 0xffffffffc0430000-0xffffffffc0431000 4K ro NX pte 0xffffffffc0431000-0xffffffffc0433000 8K RW NX pte 0xffffffffc0434000-0xffffffffc0436000 8K ro x pte 0xffffffffc0436000-0xffffffffc0438000 8K ro NX pte 0xffffffffc0438000-0xffffffffc043a000 8K RW NX pte 0xffffffffc043f000-0xffffffffc0444000 20K ro x pte 0xffffffffc0444000-0xffffffffc0447000 12K ro NX pte 0xffffffffc0447000-0xffffffffc0449000 8K RW NX pte 0xffffffffc044f000-0xffffffffc0450000 4K ro x pte 0xffffffffc0450000-0xffffffffc0451000 4K ro NX pte 0xffffffffc0451000-0xffffffffc0453000 8K RW NX pte 0xffffffffc0458000-0xffffffffc0459000 4K ro x pte 0xffffffffc0459000-0xffffffffc045b000 8K ro NX pte which is 5 lines less, but a pain to figure out the size of the holes. And it becomes even more painful when the holes go across different mapping levels. >From your 14/N changelog: > This keeps the output shorter and will help with a future change I don't care about shorter at all. It's debug information. > switching to using the generic page walk code as we no longer care about > the 'level' that the page table holes are at. I really do not understand why you think that WE no longer care about the level (and the size) of the holes. I assume that WE is pluralis majestatis and not meant to reflect the opinion of you and everyone else. I have no idea whether you ever had to do serious work with PT dump, but I surely have at various occasions including the PTI mess and I definitely found the size and the level information from holes very useful. Thanks, tglx