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From: Paul Walmsley <paul.walmsley@sifive.com>
To: Christoph Hellwig <hch@lst.de>
Cc: Palmer Dabbelt <palmer@sifive.com>,
	linux-mm@kvack.org,  Damien Le Moal <damien.lemoal@wdc.com>,
	linux-riscv@lists.infradead.org,  linux-kernel@vger.kernel.org
Subject: Re: RISC-V nommu support v2
Date: Mon, 1 Jul 2019 09:06:44 -0700 (PDT)	[thread overview]
Message-ID: <alpine.DEB.2.21.9999.1907010904320.3867@viisi.sifive.com> (raw)
In-Reply-To: <20190701065654.GA21117@lst.de>

Hi Christoph,

Probably best to feed the mm patches to Andrew.  For the RISC-V patches, 
am running a bit behind this merge window.  Combined with the end of the 
week holidays in the US, I doubt I'll make it to to the nommu series for 
v5.3.


- Paul

On Mon, 1 Jul 2019, Christoph Hellwig wrote:

> Palmer, Paul,
> 
> any comments?  Let me know if you think it is too late for 5.3
> for the full series, then I can at least feed the mm bits to
> Andrew.
> 
> On Mon, Jun 24, 2019 at 07:42:54AM +0200, Christoph Hellwig wrote:
> > Hi all,
> > 
> > below is a series to support nommu mode on RISC-V.  For now this series
> > just works under qemu with the qemu-virt platform, but Damien has also
> > been able to get kernel based on this tree with additional driver hacks
> > to work on the Kendryte KD210, but that will take a while to cleanup
> > an upstream.
> > 
> > To be useful this series also require the RISC-V binfmt_flat support,
> > which I've sent out separately.
> > 
> > A branch that includes this series and the binfmt_flat support is
> > available here:
> > 
> >     git://git.infradead.org/users/hch/riscv.git riscv-nommu.2
> > 
> > Gitweb:
> > 
> >     http://git.infradead.org/users/hch/riscv.git/shortlog/refs/heads/riscv-nommu.2
> > 
> > I've also pushed out a builtroot branch that can build a RISC-V nommu
> > root filesystem here:
> > 
> >    git://git.infradead.org/users/hch/buildroot.git riscv-nommu.2
> > 
> > Gitweb:
> > 
> >    http://git.infradead.org/users/hch/buildroot.git/shortlog/refs/heads/riscv-nommu.2
> > 
> > Changes since v1:
> >  - fixes so that a kernel with this series still work on builds with an
> >    IOMMU
> >  - small clint cleanups
> >  - the binfmt_flat base and buildroot now don't put arguments on the stack
> > 
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
> ---end quoted text---
> 



      reply	other threads:[~2019-07-01 16:06 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-24  5:42 RISC-V nommu support v2 Christoph Hellwig
2019-06-24  5:42 ` [PATCH 01/17] mm: provide a print_vma_addr stub for !CONFIG_MMU Christoph Hellwig
2019-06-24  5:42 ` [PATCH 02/17] mm: stub out all of swapops.h " Christoph Hellwig
2019-06-24  5:42 ` [PATCH 03/17] mm/nommu: fix the MAP_UNINITIALIZED flag Christoph Hellwig
2019-06-24  5:42 ` [PATCH 04/17] irqchip/sifive-plic: set max threshold for ignored handlers Christoph Hellwig
2019-06-24  5:42 ` [PATCH 05/17] riscv: use CSR_SATP instead of the legacy sptbr name in switch_mm Christoph Hellwig
2019-07-01 18:53   ` Atish Patra
2019-06-24  5:43 ` [PATCH 06/17] riscv: refactor the IPI code Christoph Hellwig
2019-06-24  5:43 ` [PATCH 07/17] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-07-01 18:37   ` Atish Patra
2019-06-24  5:43 ` [PATCH 08/17] riscv: improve the default power off implementation Christoph Hellwig
2019-07-01 21:07   ` Atish Patra
2019-06-24  5:43 ` [PATCH 09/17] riscv: provide a flat entry loader Christoph Hellwig
2019-06-24  5:43 ` [PATCH 10/17] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-07-01 21:15   ` Atish Patra
2019-06-24  5:43 ` [PATCH 11/17] riscv: provide native clint access for M-mode Christoph Hellwig
2019-06-24  5:43 ` [PATCH 12/17] riscv: implement remote sfence.i natively " Christoph Hellwig
2019-06-24  5:43 ` [PATCH 13/17] riscv: poison SBI calls " Christoph Hellwig
2019-06-24  5:43 ` [PATCH 14/17] riscv: don't allow selecting SBI-based drivers " Christoph Hellwig
2019-06-24  5:43 ` [PATCH 15/17] riscv: use the correct interrupt levels " Christoph Hellwig
2019-06-24  5:43 ` [PATCH 16/17] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-07-01 21:26   ` Atish Patra
2019-07-08  8:26     ` Palmer Dabbelt
2019-08-13 15:40       ` Christoph Hellwig
2019-08-13 15:37     ` hch
2019-06-24  5:43 ` [PATCH 17/17] riscv: add nommu support Christoph Hellwig
2019-07-12 14:52   ` Vladimir Murzin
2019-06-24 11:47 ` RISC-V nommu support v2 Vladimir Murzin
2019-06-24 11:54   ` Christoph Hellwig
2019-06-24 13:08     ` Vladimir Murzin
2019-06-24 13:16       ` Christoph Hellwig
2019-06-25  7:31       ` Palmer Dabbelt
2019-06-25 12:37         ` Vladimir Murzin
2019-07-01  6:56 ` Christoph Hellwig
2019-07-01 16:06   ` Paul Walmsley [this message]

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