Linux-mmc Archive on lore.kernel.org
 help / color / Atom feed
* [PATCH] mmc: host: sdhci-of-arasan: fix timings allocation code
@ 2020-07-14 19:12 Manish Narani
  2020-08-05  6:35 ` Ulf Hansson
  0 siblings, 1 reply; 2+ messages in thread
From: Manish Narani @ 2020-07-14 19:12 UTC (permalink / raw)
  To: michal.simek, adrian.hunter, ulf.hansson
  Cc: linux-arm-kernel, linux-mmc, linux-kernel, git, Manish Narani

The initial code that was adding delays was doing a cast over undefined
memory. This meant that the delays would be all gibberish.

This change, allocates all delays on the stack, and assigns them from the
ZynqMP & Versal macros/phase-list. And then finally copies them over the
common iclk_phase & oclk_phase variables.

Signed-off-by: Manish Narani <manish.narani@xilinx.com>
---
 drivers/mmc/host/sdhci-of-arasan.c |   25 ++++++++++++++-----------
 1 files changed, 14 insertions(+), 11 deletions(-)

diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
index db9b544..90e42d1 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -1025,7 +1025,6 @@ static void arasan_dt_read_clk_phase(struct device *dev,
 static void arasan_dt_parse_clk_phases(struct device *dev,
 				       struct sdhci_arasan_clk_data *clk_data)
 {
-	int *iclk_phase, *oclk_phase;
 	u32 mio_bank = 0;
 	int i;
 
@@ -1037,28 +1036,32 @@ static void arasan_dt_parse_clk_phases(struct device *dev,
 	clk_data->set_clk_delays = sdhci_arasan_set_clk_delays;
 
 	if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) {
-		iclk_phase = (int [MMC_TIMING_MMC_HS400 + 1]) ZYNQMP_ICLK_PHASE;
-		oclk_phase = (int [MMC_TIMING_MMC_HS400 + 1]) ZYNQMP_OCLK_PHASE;
+		u32 zynqmp_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
+			ZYNQMP_ICLK_PHASE;
+		u32 zynqmp_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
+			ZYNQMP_OCLK_PHASE;
 
 		of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank);
 		if (mio_bank == 2) {
-			oclk_phase[MMC_TIMING_UHS_SDR104] = 90;
-			oclk_phase[MMC_TIMING_MMC_HS200] = 90;
+			zynqmp_oclk_phase[MMC_TIMING_UHS_SDR104] = 90;
+			zynqmp_oclk_phase[MMC_TIMING_MMC_HS200] = 90;
 		}
 
 		for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
-			clk_data->clk_phase_in[i] = iclk_phase[i];
-			clk_data->clk_phase_out[i] = oclk_phase[i];
+			clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i];
+			clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i];
 		}
 	}
 
 	if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) {
-		iclk_phase = (int [MMC_TIMING_MMC_HS400 + 1]) VERSAL_ICLK_PHASE;
-		oclk_phase = (int [MMC_TIMING_MMC_HS400 + 1]) VERSAL_OCLK_PHASE;
+		u32 versal_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
+			VERSAL_ICLK_PHASE;
+		u32 versal_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
+			VERSAL_OCLK_PHASE;
 
 		for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
-			clk_data->clk_phase_in[i] = iclk_phase[i];
-			clk_data->clk_phase_out[i] = oclk_phase[i];
+			clk_data->clk_phase_in[i] = versal_iclk_phase[i];
+			clk_data->clk_phase_out[i] = versal_oclk_phase[i];
 		}
 	}
 
-- 
1.7.1


^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH] mmc: host: sdhci-of-arasan: fix timings allocation code
  2020-07-14 19:12 [PATCH] mmc: host: sdhci-of-arasan: fix timings allocation code Manish Narani
@ 2020-08-05  6:35 ` Ulf Hansson
  0 siblings, 0 replies; 2+ messages in thread
From: Ulf Hansson @ 2020-08-05  6:35 UTC (permalink / raw)
  To: Manish Narani
  Cc: Michal Simek, Adrian Hunter, Linux ARM, linux-mmc,
	Linux Kernel Mailing List, git

On Tue, 14 Jul 2020 at 21:12, Manish Narani <manish.narani@xilinx.com> wrote:
>
> The initial code that was adding delays was doing a cast over undefined
> memory. This meant that the delays would be all gibberish.
>
> This change, allocates all delays on the stack, and assigns them from the
> ZynqMP & Versal macros/phase-list. And then finally copies them over the
> common iclk_phase & oclk_phase variables.
>
> Signed-off-by: Manish Narani <manish.narani@xilinx.com>

Applied for next (a while ago), thanks!
Kind regards
Uffe



> ---
>  drivers/mmc/host/sdhci-of-arasan.c |   25 ++++++++++++++-----------
>  1 files changed, 14 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
> index db9b544..90e42d1 100644
> --- a/drivers/mmc/host/sdhci-of-arasan.c
> +++ b/drivers/mmc/host/sdhci-of-arasan.c
> @@ -1025,7 +1025,6 @@ static void arasan_dt_read_clk_phase(struct device *dev,
>  static void arasan_dt_parse_clk_phases(struct device *dev,
>                                        struct sdhci_arasan_clk_data *clk_data)
>  {
> -       int *iclk_phase, *oclk_phase;
>         u32 mio_bank = 0;
>         int i;
>
> @@ -1037,28 +1036,32 @@ static void arasan_dt_parse_clk_phases(struct device *dev,
>         clk_data->set_clk_delays = sdhci_arasan_set_clk_delays;
>
>         if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) {
> -               iclk_phase = (int [MMC_TIMING_MMC_HS400 + 1]) ZYNQMP_ICLK_PHASE;
> -               oclk_phase = (int [MMC_TIMING_MMC_HS400 + 1]) ZYNQMP_OCLK_PHASE;
> +               u32 zynqmp_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
> +                       ZYNQMP_ICLK_PHASE;
> +               u32 zynqmp_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
> +                       ZYNQMP_OCLK_PHASE;
>
>                 of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank);
>                 if (mio_bank == 2) {
> -                       oclk_phase[MMC_TIMING_UHS_SDR104] = 90;
> -                       oclk_phase[MMC_TIMING_MMC_HS200] = 90;
> +                       zynqmp_oclk_phase[MMC_TIMING_UHS_SDR104] = 90;
> +                       zynqmp_oclk_phase[MMC_TIMING_MMC_HS200] = 90;
>                 }
>
>                 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
> -                       clk_data->clk_phase_in[i] = iclk_phase[i];
> -                       clk_data->clk_phase_out[i] = oclk_phase[i];
> +                       clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i];
> +                       clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i];
>                 }
>         }
>
>         if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) {
> -               iclk_phase = (int [MMC_TIMING_MMC_HS400 + 1]) VERSAL_ICLK_PHASE;
> -               oclk_phase = (int [MMC_TIMING_MMC_HS400 + 1]) VERSAL_OCLK_PHASE;
> +               u32 versal_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
> +                       VERSAL_ICLK_PHASE;
> +               u32 versal_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
> +                       VERSAL_OCLK_PHASE;
>
>                 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
> -                       clk_data->clk_phase_in[i] = iclk_phase[i];
> -                       clk_data->clk_phase_out[i] = oclk_phase[i];
> +                       clk_data->clk_phase_in[i] = versal_iclk_phase[i];
> +                       clk_data->clk_phase_out[i] = versal_oclk_phase[i];
>                 }
>         }
>
> --
> 1.7.1
>

^ permalink raw reply	[flat|nested] 2+ messages in thread

end of thread, back to index

Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-14 19:12 [PATCH] mmc: host: sdhci-of-arasan: fix timings allocation code Manish Narani
2020-08-05  6:35 ` Ulf Hansson

Linux-mmc Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-mmc/0 linux-mmc/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-mmc linux-mmc/ https://lore.kernel.org/linux-mmc \
		linux-mmc@vger.kernel.org
	public-inbox-index linux-mmc

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernel.vger.linux-mmc


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git