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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id x22sm263707otk.23.2020.02.19.12.08.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Feb 2020 12:08:28 -0800 (PST) Received: (nullmailer pid 20348 invoked by uid 1000); Wed, 19 Feb 2020 20:08:27 -0000 Date: Wed, 19 Feb 2020 14:08:27 -0600 From: Rob Herring To: Veerabhadrarao Badiganti Cc: ulf.hansson@linaro.org, asutoshd@codeaurora.org, stummala@codeaurora.org, sayalil@codeaurora.org, cang@codeaurora.org, rampraka@codeaurora.org, dianders@google.com, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Mark Rutland , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" Subject: Re: [PATCH V2] dt-bindings: mmc: sdhci-msm: Add CQE reg map Message-ID: <20200219200827.GA17094@bogus> References: <1581434955-11087-1-git-send-email-vbadigan@codeaurora.org> <1581680753-9067-1-git-send-email-vbadigan@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1581680753-9067-1-git-send-email-vbadigan@codeaurora.org> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org On Fri, Feb 14, 2020 at 05:15:52PM +0530, Veerabhadrarao Badiganti wrote: > CQE feature has been enabled on sdhci-msm. Add CQE reg map > that needs to be supplied for supporting CQE feature. > > Signed-off-by: Veerabhadrarao Badiganti > --- > > Changes since V1: > - Updated description for more clarity & Fixed typos. > --- > Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt > index 7ee639b..ad0ee83 100644 > --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt > +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt > @@ -26,7 +26,13 @@ Required properties: > > - reg: Base address and length of the register in the following order: > - Host controller register map (required) > - - SD Core register map (required for msm-v4 and below) > + - SD Core register map (required for controllers earlier than msm-v5) > + - CQE register map (Optional, CQE support is present on SDHC instance meant > + for eMMC and version v4.2 and above) > +- reg-names: When CQE register map is supplied, below reg-names are required > + - "hc_mem" for Host controller register map > + - "core_mem" for SD core register map > + - "cqhci_mem" for CQE register map '_mem' is redundant, so drop. > - interrupts: Should contain an interrupt-specifiers for the interrupts: > - Host controller interrupt (required) > - pinctrl-names: Should contain only one value - "default". > -- > Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project >