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From: Andrew Jeffery <andrew@aj.id.au>
To: linux-mmc@vger.kernel.org
Cc: ulf.hansson@linaro.org, robh+dt@kernel.org, joel@jms.id.au,
	adrian.hunter@intel.com, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-aspeed@lists.ozlabs.org, ryan_chen@aspeedtech.com
Subject: [PATCH v5 0/6] mmc: sdhci-of-aspeed: Expose phase delay tuning
Date: Tue,  8 Dec 2020 11:56:09 +1030	[thread overview]
Message-ID: <20201208012615.2717412-1-andrew@aj.id.au> (raw)

Hello,

This series implements support for the MMC core clk-phase-* devicetree bindings
in the Aspeed SD/eMMC driver. The relevant register was exposed on the AST2600
and is present for both the SD/MMC controller and the dedicated eMMC
controller.

v5 fixes some build issues identified by the kernel test robot.

v4 can be found here:

https://lore.kernel.org/linux-mmc/20201207142556.2045481-1-andrew@aj.id.au/

The series has had light testing on an AST2600-based platform which requires
180deg of input and output clock phase correction at HS200, as well as some
synthetic testing under qemu and KUnit.

Please review!

Cheers,

Andrew

Andrew Jeffery (6):
  mmc: core: Add helper for parsing clock phase properties
  mmc: sdhci-of-aspeed: Expose clock phase controls
  mmc: sdhci-of-aspeed: Add AST2600 bus clock support
  mmc: sdhci-of-aspeed: Add KUnit tests for phase calculations
  MAINTAINERS: Add entry for the ASPEED SD/MMC driver
  ARM: dts: rainier: Add eMMC clock phase compensation

 MAINTAINERS                                  |   9 +
 arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts |   1 +
 drivers/mmc/core/host.c                      |  44 ++++
 drivers/mmc/host/Kconfig                     |  14 ++
 drivers/mmc/host/Makefile                    |   1 +
 drivers/mmc/host/sdhci-of-aspeed-test.c      | 100 ++++++++
 drivers/mmc/host/sdhci-of-aspeed.c           | 251 ++++++++++++++++++-
 include/linux/mmc/host.h                     |  17 ++
 8 files changed, 426 insertions(+), 11 deletions(-)
 create mode 100644 drivers/mmc/host/sdhci-of-aspeed-test.c

-- 
2.27.0


             reply	other threads:[~2020-12-08  1:27 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-08  1:26 Andrew Jeffery [this message]
2020-12-08  1:26 ` [PATCH v5 1/6] mmc: core: Add helper for parsing clock phase properties Andrew Jeffery
2020-12-14 15:48   ` Ulf Hansson
2020-12-14 23:31     ` Andrew Jeffery
2020-12-08  1:26 ` [PATCH v5 2/6] mmc: sdhci-of-aspeed: Expose clock phase controls Andrew Jeffery
2020-12-08  1:26 ` [PATCH v5 3/6] mmc: sdhci-of-aspeed: Add AST2600 bus clock support Andrew Jeffery
2020-12-08  1:26 ` [PATCH v5 4/6] mmc: sdhci-of-aspeed: Add KUnit tests for phase calculations Andrew Jeffery
2020-12-08  1:26 ` [PATCH v5 5/6] MAINTAINERS: Add entry for the ASPEED SD/MMC driver Andrew Jeffery
2020-12-08  1:26 ` [PATCH v5 6/6] ARM: dts: rainier: Add eMMC clock phase compensation Andrew Jeffery
2020-12-08  4:47   ` Joel Stanley
2020-12-14 15:56 ` [PATCH v5 0/6] mmc: sdhci-of-aspeed: Expose phase delay tuning Ulf Hansson

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