From: Eric Biggers <ebiggers@kernel.org>
To: linux-mmc@vger.kernel.org
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-fscrypt@vger.kernel.org,
Satya Tangirala <satyat@google.com>,
Ulf Hansson <ulf.hansson@linaro.org>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Adrian Hunter <adrian.hunter@intel.com>,
Asutosh Das <asutoshd@codeaurora.org>,
Rob Herring <robh+dt@kernel.org>,
Neeraj Soni <neersoni@codeaurora.org>,
Barani Muthukumaran <bmuthuku@codeaurora.org>,
Peng Zhou <peng.zhou@mediatek.com>,
Stanley Chu <stanley.chu@mediatek.com>,
Konrad Dybcio <konradybcio@gmail.com>,
Rob Herring <robh@kernel.org>
Subject: [PATCH v4 7/9] dt-bindings: mmc: sdhci-msm: add ICE registers and clock
Date: Mon, 4 Jan 2021 10:45:40 -0800 [thread overview]
Message-ID: <20210104184542.4616-8-ebiggers@kernel.org> (raw)
In-Reply-To: <20210104184542.4616-1-ebiggers@kernel.org>
From: Eric Biggers <ebiggers@google.com>
Document the bindings for the registers and clock for the MMC instance
of the Inline Crypto Engine (ICE) on Snapdragon SoCs. These bindings
are needed in order for sdhci-msm to support inline encryption.
Reviewed-by: Satya Tangirala <satyat@google.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Eric Biggers <ebiggers@google.com>
---
Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
index 3b602fd6180bf..4f2e138439506 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
+++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
@@ -30,10 +30,12 @@ Required properties:
- SD Core register map (required for controllers earlier than msm-v5)
- CQE register map (Optional, CQE support is present on SDHC instance meant
for eMMC and version v4.2 and above)
+ - Inline Crypto Engine register map (optional)
- reg-names: When CQE register map is supplied, below reg-names are required
- "hc" for Host controller register map
- "core" for SD core register map
- "cqhci" for CQE register map
+ - "ice" for Inline Crypto Engine register map (optional)
- interrupts: Should contain an interrupt-specifiers for the interrupts:
- Host controller interrupt (required)
- pinctrl-names: Should contain only one value - "default".
@@ -46,6 +48,7 @@ Required properties:
"xo" - TCXO clock (optional)
"cal" - reference clock for RCLK delay calibration (optional)
"sleep" - sleep clock for RCLK delay calibration (optional)
+ "ice" - clock for Inline Crypto Engine (optional)
- qcom,ddr-config: Certain chipsets and platforms require particular settings
for the DDR_CONFIG register. Use this field to specify the register
--
2.30.0
next prev parent reply other threads:[~2021-01-04 18:49 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-04 18:45 [PATCH v4 0/9] eMMC inline encryption support Eric Biggers
2021-01-04 18:45 ` [PATCH v4 1/9] mmc: add basic support for inline encryption Eric Biggers
2021-01-15 9:22 ` Ulf Hansson
2021-01-15 17:56 ` Eric Biggers
2021-01-18 14:21 ` Ulf Hansson
2021-01-19 20:51 ` Eric Biggers
2021-01-21 7:45 ` Eric Biggers
2021-01-21 9:18 ` Eric Biggers
2021-01-21 13:08 ` Ulf Hansson
2021-01-04 18:45 ` [PATCH v4 2/9] mmc: cqhci: rename cqhci.c to cqhci-core.c Eric Biggers
2021-01-04 18:45 ` [PATCH v4 3/9] mmc: cqhci: initialize upper 64 bits of 128-bit task descriptors Eric Biggers
2021-01-04 18:45 ` [PATCH v4 4/9] mmc: cqhci: add support for inline encryption Eric Biggers
2021-01-04 18:45 ` [PATCH v4 5/9] mmc: cqhci: add cqhci_host_ops::program_key Eric Biggers
2021-01-04 18:45 ` [PATCH v4 6/9] firmware: qcom_scm: update comment for ICE-related functions Eric Biggers
2021-01-04 18:45 ` Eric Biggers [this message]
2021-01-04 18:45 ` [PATCH v4 8/9] arm64: dts: qcom: sdm630: add ICE registers and clocks Eric Biggers
2021-01-04 18:45 ` [PATCH v4 9/9] mmc: sdhci-msm: add Inline Crypto Engine support Eric Biggers
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