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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 May 2023 22:04:22.1124 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6d6e20a6-e6b4-478d-0596-08db6159d2ea X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT089.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6259 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Hi Geert, On Wed, May 24, 2023 at 13:52 Geert Uytterhoeven wrote: > On Tue, May 23, 2023 at 9:30 PM Brad Larson wrote: >> On 5/16/23 09:54, Michal Simek wrote: >> > On 5/15/23 20:16, Brad Larson wrote: >> >> --- /dev/null >> >> +++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi >> >> @@ -0,0 +1,197 @@ >> >> +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) >> >> +/* >> >> + * Copyright 2020-2022 Advanced Micro Devices, Inc. >> > >> > 2023 and the same below. >> >> I'll update the copyright in the next submit > > Did you make any substantial changes in 2023? Yes, additional properties were added to l2-cache* >> >> + */ >> >> + >> >> +/ { >> >> + cpus { >> >> + #address-cells = <2>; >> >> + #size-cells = <0>; >> >> + >> >> + cpu-map { >> >> + cluster0 { >> >> + core0 { cpu = <&cpu0>; }; >> >> + core1 { cpu = <&cpu1>; }; >> >> + core2 { cpu = <&cpu2>; }; >> >> + core3 { cpu = <&cpu3>; }; >> >> + }; >> >> + >> >> + cluster1 { >> >> + core0 { cpu = <&cpu4>; }; >> >> + core1 { cpu = <&cpu5>; }; >> >> + core2 { cpu = <&cpu6>; }; >> >> + core3 { cpu = <&cpu7>; }; >> >> + }; >> >> + >> >> + cluster2 { >> >> + core0 { cpu = <&cpu8>; }; >> >> + core1 { cpu = <&cpu9>; }; >> >> + core2 { cpu = <&cpu10>; }; >> >> + core3 { cpu = <&cpu11>; }; >> >> + }; >> >> + >> >> + cluster3 { >> >> + core0 { cpu = <&cpu12>; }; >> >> + core1 { cpu = <&cpu13>; }; >> >> + core2 { cpu = <&cpu14>; }; >> >> + core3 { cpu = <&cpu15>; }; >> >> + }; >> >> + }; >> >> + >> >> + /* CLUSTER 0 */ >> >> + cpu0: cpu@0 { >> >> + device_type = "cpu"; >> >> + compatible = "arm,cortex-a72"; >> >> + reg = <0 0x0>; >> > >> > Do you really need 2/0 split here. The first cell is 0 anyway. >> >> Yes following 64-bit system definition > > You mean for the 64-bit main address space? > The CPU address space under /cpus is unrelated. Yes, the reg prop for this node is CPU/threads per dt spec. Checked the history and the Elba dt was derived from socionext for these nodes and this is how those device trees are configured along with over a dozen other devices. I changed to address-cells = <1> and dropped the leading zero from all cpu* reg<> and booting the system I'm observing no change. Looking in drivers/of I'm not seeing where cpu*/reg is read and used, any recommendation? >> >> +++ b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi >> >> @@ -0,0 +1,106 @@ >> >> +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) >> >> +/* >> >> + * Copyright 2020-2022 Advanced Micro Devices, Inc. >> >> + */ >> >> + >> >> +&flash0 { >> 0xf0000>> + partitions { >> >> + compatible = "fixed-partitions"; >> >> + #address-cells = <1>; >> >> + #size-cells = <1>; >> >> + partition@0 { >> >> + label = "flash"; >> >> + reg = <0x10000 0xfff0000>; >> > >> > This doesn't fit with partition@0 above. >> > Also size is weird. >> >> This is intended to not expose sector 0. > > The unit address should still match the first reg entry > => partition@10000. Changed to this: partition@0 { label = "rsvd"; reg = <0x0 0x10000>; read-only; }; partition@10000 { label = "flash"; reg = <0x10000 0xfff0000>; }; Regards, Brad