From: Komal Bajaj <quic_kbajaj@quicinc.com>
To: Ulf Hansson <ulf.hansson@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Bhupesh Sharma <bhupesh.sharma@linaro.org>
Cc: Komal Bajaj <quic_kbajaj@quicinc.com>,
linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org
Subject: [PATCH v4 2/4] arm64: dts: qcom: qdu1000: Add SDHCI node
Date: Thu, 1 Jun 2023 12:28:03 +0530 [thread overview]
Message-ID: <20230601065805.18079-3-quic_kbajaj@quicinc.com> (raw)
In-Reply-To: <20230601065805.18079-1-quic_kbajaj@quicinc.com>
Add sdhc node for eMMC on QDU1000 and QRU1000 SoCs.
Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
---
arch/arm64/boot/dts/qcom/qdu1000.dtsi | 47 +++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
index 734438113bba..6df07334f1d3 100644
--- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
@@ -842,6 +842,53 @@
#hwlock-cells = <1>;
};
+ sdhc: mmc@8804000 {
+ compatible = "qcom,qdu1000-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x08804000 0x0 0x1000>,
+ <0x0 0x08805000 0x0 0x1000>;
+ reg-names = "hc", "cqhci";
+
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC5_AHB_CLK>,
+ <&gcc GCC_SDCC5_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface",
+ "core",
+ "xo";
+
+ resets = <&gcc GCC_SDCC5_BCR>;
+
+ interconnects = <&system_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_SDCC_2 0>;
+ interconnect-names = "sdhc-ddr", "cpu-sdhc";
+ power-domains = <&rpmhpd QDU1000_CX>;
+ operating-points-v2 = <&sdhc1_opp_table>;
+
+ iommus = <&apps_smmu 0x80 0x0>;
+ dma-coherent;
+
+ bus-width = <8>;
+
+ qcom,dll-config = <0x0007642c>;
+ qcom,ddr-config = <0x80040868>;
+
+ status = "disabled";
+
+ sdhc1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <6528000 1652800>;
+ opp-avg-kBps = <400000 0>;
+ };
+ };
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,qdu1000-pdc", "qcom,pdc";
reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
--
2.17.1
next prev parent reply other threads:[~2023-06-01 6:58 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-01 6:58 [PATCH v4 0/4] arm64: dts: qcom: qdu1000: add SDHCI Komal Bajaj
2023-06-01 6:58 ` [PATCH v4 1/4] dt-bindings: mmc: sdhci-msm: Document the QDU1000/QRU1000 compatible Komal Bajaj
2023-06-01 6:58 ` Komal Bajaj [this message]
2023-06-01 8:27 ` [PATCH v4 2/4] arm64: dts: qcom: qdu1000: Add SDHCI node Konrad Dybcio
2023-06-01 6:58 ` [PATCH v4 3/4] arm64: dts: qcom: qdu1000: Add SDHCI pin configuration to DTSI Komal Bajaj
2023-06-01 7:00 ` Krzysztof Kozlowski
2023-06-01 8:28 ` Konrad Dybcio
2023-06-01 8:48 ` Komal Bajaj
2023-06-01 8:27 ` Konrad Dybcio
2023-06-01 6:58 ` [PATCH v4 4/4] arm64: dts: qcom: qdu1000-idp: add SDHCI for emmc Komal Bajaj
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