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bh=A9dUMlaBrYr0QPUU+/BwByH9mR1EJj9X/+BxAnd7n7g=; b=SVwHqe3Tj13HSf3asA8xWHQI1K+9sLDwPZONHo4pg+P2Lb72mTW+oDnN7RFkQEePZD a4J0MXl2K/ghDCEbyLj/u4tm5tGBjYGWbx8jGpvX+fQjpJ2BF4u1VTeusS9UPdOOu48y cNzmipjeFqsXw058xjQ9kqmcu7Mj2q/nbROAnXd7ML9R1axlDfbel3kYPjeQD+CnvjB4 Rw//65kul7ZchNS4EHgZouUYK1B71bxXhmSpR3xSx/UNBSe4QvwRWz7hy8fooRpS9zbL mGVAlc9UvjiJTyH2INOTMXjnPKCO0LjfYeR2/Ca+qZlQI6lNA/CLjquCC+dOg0/lUvWl Z23g== X-Gm-Message-State: AOAM530fU60Wpi/AhRVMdOALSbE8FwCOQ18vP292esNj8uKroL6D0nUz 1iyZ+16ETjWSiuJVtIL5MShvrKoZwYOBaosSFDY9yvNr0FdK7A== X-Google-Smtp-Source: ABdhPJyq3iaF9iHmf1FP2YZmUz8+m0tjz+LBxu2zhSgpmuNGB3x9iwVpZxb6Icf9nxJJqlL9tdZw9y4dFEqmdQmH7ik= X-Received: by 2002:a67:8c06:: with SMTP id o6mr5056875vsd.200.1598340862095; Tue, 25 Aug 2020 00:34:22 -0700 (PDT) MIME-Version: 1.0 References: <20200824151035.31093-1-lars.povlsen@microchip.com> <20200824151035.31093-2-lars.povlsen@microchip.com> In-Reply-To: <20200824151035.31093-2-lars.povlsen@microchip.com> From: Ulf Hansson Date: Tue, 25 Aug 2020 09:33:45 +0200 Message-ID: Subject: Re: [PATCH v4 1/3] dt-bindings: mmc: Add Sparx5 SDHCI controller bindings To: Lars Povlsen List-Id: Cc: Adrian Hunter , SoC Team , Rob Herring , Microchip Linux Driver Support , "linux-mmc@vger.kernel.org" , DTML , Linux ARM , Linux Kernel Mailing List , Alexandre Belloni Content-Type: text/plain; charset="UTF-8" Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org On Mon, 24 Aug 2020 at 17:10, Lars Povlsen wrote: > > The Sparx5 SDHCI controller is based on the Designware controller IP. > > Signed-off-by: Lars Povlsen > --- > .../mmc/microchip,dw-sparx5-sdhci.yaml | 65 +++++++++++++++++++ > 1 file changed, 65 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml > > diff --git a/Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml b/Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml > new file mode 100644 > index 0000000000000..55883290543b9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml > @@ -0,0 +1,65 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mmc/microchip,dw-sparx5-sdhci.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip Sparx5 Mobile Storage Host Controller Binding > + > +allOf: > + - $ref: "mmc-controller.yaml" > + > +maintainers: > + - Lars Povlsen > + > +# Everything else is described in the common file > +properties: > + compatible: > + const: microchip,dw-sparx5-sdhci > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + description: > + Handle to "core" clock for the sdhci controller. > + > + clock-names: > + items: > + - const: core > + > + microchip,clock-delay: > + description: Delay clock to card to meet setup time requirements. > + Each step increase by 1.25ns. > + $ref: "/schemas/types.yaml#/definitions/uint32" > + minimum: 1 > + maximum: 15 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + > +examples: > + - | > + #include > + #include > + sdhci0: mmc@600800000 { Nitpick: I think we should use solely "mmc[n]" here. So: mmc0@600800000 { Please update patch3/3 accordingly as well. > + compatible = "microchip,dw-sparx5-sdhci"; > + reg = <0x00800000 0x1000>; > + pinctrl-0 = <&emmc_pins>; > + pinctrl-names = "default"; > + clocks = <&clks CLK_ID_AUX1>; > + clock-names = "core"; > + assigned-clocks = <&clks CLK_ID_AUX1>; > + assigned-clock-rates = <800000000>; > + interrupts = ; > + bus-width = <8>; > + microchip,clock-delay = <10>; > + }; Kind regards Uffe