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bh=XXBH4sOkqPl9zJcXTUASMt/Fu8TtonsFgui8Kl7kFVY=; b=RR0bkcegHtxnGDOqav8IKPrH/LEUhDiJmnd+MaZiMpKEH8E/RMzMYn5uPkhHmyCDlw 8bFEXk3lInm7CyiiSXBU6sbKFdjW8U9o91t5x7HqoDcFG6g+UxLrk4DQVWI48JEAYsS+ c3L/XOC56p/mV5cAXRfjQFPsmKInQ8gUIbaLmbRcSK3c4sf3CbtJeqxlglVF3ogXHafO RRgvJty3BeKm+wY/GRahipvKfOzD/6Pu84AH+xjC862kzmlAvAndIHQSUfpgOdo0YPlJ I0xvGaQSYfV2GPmBv4cnKzmErao4xIqXQmOZwzby9OIl6UxAuRa1O7N4LorohQueuiYk cQXg== X-Gm-Message-State: AOAM532ey8ejzcYyo1x0ytfHNb2R2Iiy1NW/9X6sJ1hCoZqs+UnrxX8f ClSm0lRoeDgjaBRB19w0I43GvKmYmT8dC9FjPTXfRg== X-Google-Smtp-Source: ABdhPJzPB9driK8H4qkeuT9S/aH4aByKHE7EXpTg6JCgldVacqxODAO1rUsFRonHGhpGwdxbkweJVIM8uPGeKAfsn/U= X-Received: by 2002:a67:8c06:: with SMTP id o6mr5214822vsd.200.1598347574303; Tue, 25 Aug 2020 02:26:14 -0700 (PDT) MIME-Version: 1.0 References: <20200824151035.31093-1-lars.povlsen@microchip.com> <20200824151035.31093-2-lars.povlsen@microchip.com> <20200825084752.GD2389103@piout.net> In-Reply-To: <20200825084752.GD2389103@piout.net> From: Ulf Hansson Date: Tue, 25 Aug 2020 11:25:37 +0200 Message-ID: Subject: Re: [PATCH v4 1/3] dt-bindings: mmc: Add Sparx5 SDHCI controller bindings To: Alexandre Belloni List-Id: Cc: Lars Povlsen , Adrian Hunter , SoC Team , Rob Herring , Microchip Linux Driver Support , "linux-mmc@vger.kernel.org" , DTML , Linux ARM , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org On Tue, 25 Aug 2020 at 10:47, Alexandre Belloni wrote: > > On 25/08/2020 09:33:45+0200, Ulf Hansson wrote: > > On Mon, 24 Aug 2020 at 17:10, Lars Povlsen wrote: > > > > > > The Sparx5 SDHCI controller is based on the Designware controller IP. > > > > > > Signed-off-by: Lars Povlsen > > > --- > > > .../mmc/microchip,dw-sparx5-sdhci.yaml | 65 +++++++++++++++++++ > > > 1 file changed, 65 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml b/Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml > > > new file mode 100644 > > > index 0000000000000..55883290543b9 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml > > > @@ -0,0 +1,65 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/mmc/microchip,dw-sparx5-sdhci.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Microchip Sparx5 Mobile Storage Host Controller Binding > > > + > > > +allOf: > > > + - $ref: "mmc-controller.yaml" > > > + > > > +maintainers: > > > + - Lars Povlsen > > > + > > > +# Everything else is described in the common file > > > +properties: > > > + compatible: > > > + const: microchip,dw-sparx5-sdhci > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + interrupts: > > > + maxItems: 1 > > > + > > > + clocks: > > > + maxItems: 1 > > > + description: > > > + Handle to "core" clock for the sdhci controller. > > > + > > > + clock-names: > > > + items: > > > + - const: core > > > + > > > + microchip,clock-delay: > > > + description: Delay clock to card to meet setup time requirements. > > > + Each step increase by 1.25ns. > > > + $ref: "/schemas/types.yaml#/definitions/uint32" > > > + minimum: 1 > > > + maximum: 15 > > > + > > > +required: > > > + - compatible > > > + - reg > > > + - interrupts > > > + - clocks > > > + - clock-names > > > + > > > +examples: > > > + - | > > > + #include > > > + #include > > > + sdhci0: mmc@600800000 { > > > > Nitpick: > > > > I think we should use solely "mmc[n]" here. So: > > > > mmc0@600800000 { > > > > Please update patch3/3 accordingly as well. > > This is not what the devicetree specification says. 2.2.2 says that the > generic name is mmc, not mmc[n]. Since there is a proper unit-address, I > don't see the need for an index here. You are absolutely right, thanks! My apologies for the noise! > > > > > > + compatible = "microchip,dw-sparx5-sdhci"; > > > + reg = <0x00800000 0x1000>; > > > + pinctrl-0 = <&emmc_pins>; > > > + pinctrl-names = "default"; > > > + clocks = <&clks CLK_ID_AUX1>; > > > + clock-names = "core"; > > > + assigned-clocks = <&clks CLK_ID_AUX1>; > > > + assigned-clock-rates = <800000000>; > > > + interrupts = ; > > > + bus-width = <8>; > > > + microchip,clock-delay = <10>; > > > + }; Kind regards Uffe