[PATCH 0/4] Enhancements and Bug Fixes in ZynqMP SDHCI

[PATCH 0/4] Enhancements and Bug Fixes in ZynqMP SDHCI

[Manish Narani]

This patch series includes:
-> Mark the Tap Delay Node as valid for ioctl calls
-> Add support for DLL reset in firmware driver
-> Add support to reset DLL from Arasan SDHCI driver for ZynqMP platform
-> Fix incorrect base clock reporting issue

Manish Narani (4):
  firmware: xilinx: Add ZynqMP Tap Delay setup ioctl to the valid list
  firmware: xilinx: Add DLL reset support
  mmc: sdhci-of-arasan: Add support for DLL reset for ZynqMP platforms
  sdhci: arasan: Remove quirk for broken base clock

 drivers/firmware/xilinx/zynqmp.c     |  2 +
 drivers/mmc/host/sdhci-of-arasan.c   | 59 +++++++++++++++++++++++++++-
 include/linux/firmware/xlnx-zynqmp.h |  9 ++++-
 3 files changed, 68 insertions(+), 2 deletions(-)

-- 
2.17.1

[PATCH 1/4] firmware: xilinx: Add ZynqMP Tap Delay setup ioctl to the valid list

[Manish Narani]

The Tap Delay setup ioctl was not added to valid list due to which it
may fail to set Tap Delays for SD. This patch fixes the same.

Signed-off-by: Manish Narani <manish.narani@xilinx.com>
---
 drivers/firmware/xilinx/zynqmp.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 75bdfaa08380..89eb198cee5e 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -469,6 +469,7 @@ static int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
 static inline int zynqmp_is_valid_ioctl(u32 ioctl_id)
 {
 	switch (ioctl_id) {
+	case IOCTL_SET_SD_TAPDELAY:
 	case IOCTL_SET_PLL_FRAC_MODE:
 	case IOCTL_GET_PLL_FRAC_MODE:
 	case IOCTL_SET_PLL_FRAC_DATA:
-- 
2.17.1

[PATCH 2/4] firmware: xilinx: Add DLL reset support

[Manish Narani]

SD DLL resets are required for some of the operations on ZynqMP platform.
Add DLL reset support in ZynqMP firmware driver for SD DLL reset.

Signed-off-by: Manish Narani <manish.narani@xilinx.com>
---
 drivers/firmware/xilinx/zynqmp.c     | 1 +
 include/linux/firmware/xlnx-zynqmp.h | 9 ++++++++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 89eb198cee5e..165ec0f1e10a 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -469,6 +469,7 @@ static int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
 static inline int zynqmp_is_valid_ioctl(u32 ioctl_id)
 {
 	switch (ioctl_id) {
+	case IOCTL_SD_DLL_RESET:
 	case IOCTL_SET_SD_TAPDELAY:
 	case IOCTL_SET_PLL_FRAC_MODE:
 	case IOCTL_GET_PLL_FRAC_MODE:
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index e41ad9e37136..01a6d972b8a8 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -92,7 +92,8 @@ enum pm_ret_status {
 };
 
 enum pm_ioctl_id {
-	IOCTL_SET_SD_TAPDELAY = 7,
+	IOCTL_SD_DLL_RESET = 6,
+	IOCTL_SET_SD_TAPDELAY,
 	IOCTL_SET_PLL_FRAC_MODE,
 	IOCTL_GET_PLL_FRAC_MODE,
 	IOCTL_SET_PLL_FRAC_DATA,
@@ -262,6 +263,12 @@ enum tap_delay_type {
 	PM_TAPDELAY_OUTPUT,
 };
 
+enum dll_reset_type {
+	PM_DLL_RESET_ASSERT,
+	PM_DLL_RESET_RELEASE,
+	PM_DLL_RESET_PULSE,
+};
+
 /**
  * struct zynqmp_pm_query_data - PM query data
  * @qid:	query ID
-- 
2.17.1

[PATCH 3/4] mmc: sdhci-of-arasan: Add support for DLL reset for ZynqMP platforms

[Manish Narani]

The DLL resets are required while executing the auto tuning procedure in
ZynqMP. This patch adds code to support the same.

Signed-off-by: Manish Narani <manish.narani@xilinx.com>
---
 drivers/mmc/host/sdhci-of-arasan.c | 46 ++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
index e49b44b4d82e..39176ab5ca1f 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -757,6 +757,50 @@ static const struct clk_ops zynqmp_sampleclk_ops = {
 	.set_phase = sdhci_zynqmp_sampleclk_set_phase,
 };
 
+static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
+	struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data =
+		sdhci_arasan->clk_data.clk_of_data;
+	const struct zynqmp_eemi_ops *eemi_ops = zynqmp_clk_data->eemi_ops;
+	u16 clk;
+
+	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+	clk &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
+	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+	/* Issue DLL Reset */
+	eemi_ops->ioctl(deviceid, IOCTL_SD_DLL_RESET,
+			PM_DLL_RESET_PULSE, 0, NULL);
+
+	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+
+	sdhci_enable_clk(host, clk);
+}
+
+static int arasan_zynqmp_execute_tuning(struct mmc_host *mmc, u32 opcode)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
+	struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw;
+	const char *clk_name = clk_hw_get_name(hw);
+	u32 device_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 :
+							   NODE_SD_1;
+	int err;
+
+	arasan_zynqmp_dll_reset(host, device_id);
+
+	err = sdhci_execute_tuning(mmc, opcode);
+	if (err)
+		return err;
+
+	arasan_zynqmp_dll_reset(host, device_id);
+
+	return 0;
+}
+
 /**
  * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
  *
@@ -1247,6 +1291,8 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
 
 		zynqmp_clk_data->eemi_ops = eemi_ops;
 		sdhci_arasan->clk_data.clk_of_data = zynqmp_clk_data;
+		host->mmc_host_ops.execute_tuning =
+			arasan_zynqmp_execute_tuning;
 	}
 
 	arasan_dt_parse_clk_phases(&pdev->dev, &sdhci_arasan->clk_data);
-- 
2.17.1

[PATCH 4/4] sdhci: arasan: Remove quirk for broken base clock

[Manish Narani]

This patch removes quirk which indicates a broken base clock. This was
making the kernel report wrong base clock of ~187MHz instead of 200MHz
even as the measurement on the hardware was showing 200MHz.

Signed-off-by: Manish Narani <manish.narani@xilinx.com>
State: pending
---
 drivers/mmc/host/sdhci-of-arasan.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
index 39176ab5ca1f..0146d7dd315b 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -358,6 +358,17 @@ static struct sdhci_arasan_of_data sdhci_arasan_data = {
 	.pdata = &sdhci_arasan_pdata,
 };
 
+static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = {
+	.ops = &sdhci_arasan_ops,
+	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
+			SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
+			SDHCI_QUIRK2_STOP_WITH_TC,
+};
+
+static struct sdhci_arasan_of_data sdhci_arasan_zynqmp_data = {
+	.pdata = &sdhci_arasan_zynqmp_pdata,
+};
+
 static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask)
 {
 	int cmd_error = 0;
@@ -553,7 +564,7 @@ static const struct of_device_id sdhci_arasan_of_match[] = {
 	},
 	{
 		.compatible = "xlnx,zynqmp-8.9a",
-		.data = &sdhci_arasan_data,
+		.data = &sdhci_arasan_zynqmp_data,
 	},
 	{ /* sentinel */ }
 };
-- 
2.17.1

RE: [PATCH 0/4] Enhancements and Bug Fixes in ZynqMP SDHCI

[Manish Narani]

Ping!

> -----Original Message-----
> From: Manish Narani <manish.narani@xilinx.com>
> Sent: Tuesday, January 21, 2020 3:52 PM
> To: Michal Simek <michals@xilinx.com>; adrian.hunter@intel.com;
> ulf.hansson@linaro.org; Jolly Shah <JOLLYS@xilinx.com>; Rajan Vaja
> <RAJANV@xilinx.com>; Nava kishore Manne <navam@xilinx.com>; Manish
> Narani <MNARANI@xilinx.com>; Tejas Patel <TEJASP@xilinx.com>
> Cc: linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
> mmc@vger.kernel.org
> Subject: [PATCH 0/4] Enhancements and Bug Fixes in ZynqMP SDHCI
> 
> This patch series includes:
> -> Mark the Tap Delay Node as valid for ioctl calls
> -> Add support for DLL reset in firmware driver
> -> Add support to reset DLL from Arasan SDHCI driver for ZynqMP platform
> -> Fix incorrect base clock reporting issue
> 
> Manish Narani (4):
>   firmware: xilinx: Add ZynqMP Tap Delay setup ioctl to the valid list
>   firmware: xilinx: Add DLL reset support
>   mmc: sdhci-of-arasan: Add support for DLL reset for ZynqMP platforms
>   sdhci: arasan: Remove quirk for broken base clock
> 
>  drivers/firmware/xilinx/zynqmp.c     |  2 +
>  drivers/mmc/host/sdhci-of-arasan.c   | 59 +++++++++++++++++++++++++++-
>  include/linux/firmware/xlnx-zynqmp.h |  9 ++++-
>  3 files changed, 68 insertions(+), 2 deletions(-)
> 
> --
> 2.17.1

Re: [PATCH 4/4] sdhci: arasan: Remove quirk for broken base clock

[Adrian Hunter]

On 21/01/20 12:21 pm, Manish Narani wrote:
> This patch removes quirk which indicates a broken base clock. This was
> making the kernel report wrong base clock of ~187MHz instead of 200MHz
> even as the measurement on the hardware was showing 200MHz.
> 
> Signed-off-by: Manish Narani <manish.narani@xilinx.com>
> State: pending

Huh?

Otherwise:

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci-of-arasan.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
> index 39176ab5ca1f..0146d7dd315b 100644
> --- a/drivers/mmc/host/sdhci-of-arasan.c
> +++ b/drivers/mmc/host/sdhci-of-arasan.c
> @@ -358,6 +358,17 @@ static struct sdhci_arasan_of_data sdhci_arasan_data = {
>  	.pdata = &sdhci_arasan_pdata,
>  };
>  
> +static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = {
> +	.ops = &sdhci_arasan_ops,
> +	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
> +			SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
> +			SDHCI_QUIRK2_STOP_WITH_TC,
> +};
> +
> +static struct sdhci_arasan_of_data sdhci_arasan_zynqmp_data = {
> +	.pdata = &sdhci_arasan_zynqmp_pdata,
> +};
> +
>  static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask)
>  {
>  	int cmd_error = 0;
> @@ -553,7 +564,7 @@ static const struct of_device_id sdhci_arasan_of_match[] = {
>  	},
>  	{
>  		.compatible = "xlnx,zynqmp-8.9a",
> -		.data = &sdhci_arasan_data,
> +		.data = &sdhci_arasan_zynqmp_data,
>  	},
>  	{ /* sentinel */ }
>  };
> 

Re: [PATCH 3/4] mmc: sdhci-of-arasan: Add support for DLL reset for ZynqMP platforms

[Adrian Hunter]

On 21/01/20 12:21 pm, Manish Narani wrote:
> The DLL resets are required while executing the auto tuning procedure in
> ZynqMP. This patch adds code to support the same.
> 
> Signed-off-by: Manish Narani <manish.narani@xilinx.com>

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci-of-arasan.c | 46 ++++++++++++++++++++++++++++++
>  1 file changed, 46 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
> index e49b44b4d82e..39176ab5ca1f 100644
> --- a/drivers/mmc/host/sdhci-of-arasan.c
> +++ b/drivers/mmc/host/sdhci-of-arasan.c
> @@ -757,6 +757,50 @@ static const struct clk_ops zynqmp_sampleclk_ops = {
>  	.set_phase = sdhci_zynqmp_sampleclk_set_phase,
>  };
>  
> +static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
> +	struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data =
> +		sdhci_arasan->clk_data.clk_of_data;
> +	const struct zynqmp_eemi_ops *eemi_ops = zynqmp_clk_data->eemi_ops;
> +	u16 clk;
> +
> +	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
> +	clk &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
> +	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
> +
> +	/* Issue DLL Reset */
> +	eemi_ops->ioctl(deviceid, IOCTL_SD_DLL_RESET,
> +			PM_DLL_RESET_PULSE, 0, NULL);
> +
> +	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
> +
> +	sdhci_enable_clk(host, clk);
> +}
> +
> +static int arasan_zynqmp_execute_tuning(struct mmc_host *mmc, u32 opcode)
> +{
> +	struct sdhci_host *host = mmc_priv(mmc);
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
> +	struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw;
> +	const char *clk_name = clk_hw_get_name(hw);
> +	u32 device_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 :
> +							   NODE_SD_1;
> +	int err;
> +
> +	arasan_zynqmp_dll_reset(host, device_id);
> +
> +	err = sdhci_execute_tuning(mmc, opcode);
> +	if (err)
> +		return err;
> +
> +	arasan_zynqmp_dll_reset(host, device_id);
> +
> +	return 0;
> +}
> +
>  /**
>   * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
>   *
> @@ -1247,6 +1291,8 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
>  
>  		zynqmp_clk_data->eemi_ops = eemi_ops;
>  		sdhci_arasan->clk_data.clk_of_data = zynqmp_clk_data;
> +		host->mmc_host_ops.execute_tuning =
> +			arasan_zynqmp_execute_tuning;
>  	}
>  
>  	arasan_dt_parse_clk_phases(&pdev->dev, &sdhci_arasan->clk_data);
> 

Re: [PATCH 1/4] firmware: xilinx: Add ZynqMP Tap Delay setup ioctl to the valid list

[Michal Simek]

On 21. 01. 20 11:21, Manish Narani wrote:
> The Tap Delay setup ioctl was not added to valid list due to which it
> may fail to set Tap Delays for SD. This patch fixes the same.
> 
> Signed-off-by: Manish Narani <manish.narani@xilinx.com>
> ---
>  drivers/firmware/xilinx/zynqmp.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
> index 75bdfaa08380..89eb198cee5e 100644
> --- a/drivers/firmware/xilinx/zynqmp.c
> +++ b/drivers/firmware/xilinx/zynqmp.c
> @@ -469,6 +469,7 @@ static int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
>  static inline int zynqmp_is_valid_ioctl(u32 ioctl_id)
>  {
>  	switch (ioctl_id) {
> +	case IOCTL_SET_SD_TAPDELAY:
>  	case IOCTL_SET_PLL_FRAC_MODE:
>  	case IOCTL_GET_PLL_FRAC_MODE:
>  	case IOCTL_SET_PLL_FRAC_DATA:
> 

Acked-by: Michal Simek <michal.simek@xilinx.com>

Thanks,
Michal

Re: [PATCH 2/4] firmware: xilinx: Add DLL reset support

[Michal Simek]

On 21. 01. 20 11:21, Manish Narani wrote:
> SD DLL resets are required for some of the operations on ZynqMP platform.
> Add DLL reset support in ZynqMP firmware driver for SD DLL reset.
> 
> Signed-off-by: Manish Narani <manish.narani@xilinx.com>
> ---
>  drivers/firmware/xilinx/zynqmp.c     | 1 +
>  include/linux/firmware/xlnx-zynqmp.h | 9 ++++++++-
>  2 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
> index 89eb198cee5e..165ec0f1e10a 100644
> --- a/drivers/firmware/xilinx/zynqmp.c
> +++ b/drivers/firmware/xilinx/zynqmp.c
> @@ -469,6 +469,7 @@ static int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
>  static inline int zynqmp_is_valid_ioctl(u32 ioctl_id)
>  {
>  	switch (ioctl_id) {
> +	case IOCTL_SD_DLL_RESET:
>  	case IOCTL_SET_SD_TAPDELAY:
>  	case IOCTL_SET_PLL_FRAC_MODE:
>  	case IOCTL_GET_PLL_FRAC_MODE:
> diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
> index e41ad9e37136..01a6d972b8a8 100644
> --- a/include/linux/firmware/xlnx-zynqmp.h
> +++ b/include/linux/firmware/xlnx-zynqmp.h
> @@ -92,7 +92,8 @@ enum pm_ret_status {
>  };
>  
>  enum pm_ioctl_id {
> -	IOCTL_SET_SD_TAPDELAY = 7,
> +	IOCTL_SD_DLL_RESET = 6,
> +	IOCTL_SET_SD_TAPDELAY,
>  	IOCTL_SET_PLL_FRAC_MODE,
>  	IOCTL_GET_PLL_FRAC_MODE,
>  	IOCTL_SET_PLL_FRAC_DATA,
> @@ -262,6 +263,12 @@ enum tap_delay_type {
>  	PM_TAPDELAY_OUTPUT,
>  };
>  
> +enum dll_reset_type {
> +	PM_DLL_RESET_ASSERT,
> +	PM_DLL_RESET_RELEASE,
> +	PM_DLL_RESET_PULSE,
> +};
> +
>  /**
>   * struct zynqmp_pm_query_data - PM query data
>   * @qid:	query ID
> 

Acked-by: Michal Simek <michal.simek@xilinx.com>

Thanks,
Michal

Re: [PATCH 4/4] sdhci: arasan: Remove quirk for broken base clock

[Michal Simek]

On 03. 02. 20 12:31, Adrian Hunter wrote:
> On 21/01/20 12:21 pm, Manish Narani wrote:
>> This patch removes quirk which indicates a broken base clock. This was
>> making the kernel report wrong base clock of ~187MHz instead of 200MHz
>> even as the measurement on the hardware was showing 200MHz.
>>
>> Signed-off-by: Manish Narani <manish.narani@xilinx.com>
>> State: pending
> 
> Huh?

It shouldn't be here. It is internal patch labeling.
Manish: Please send v2 with all lines you got and remove this above.

> 
> Otherwise:
> 
> Acked-by: Adrian Hunter <adrian.hunter@intel.com>

These patches requires firmware changes. Feel free to take it directly
via your tree. If you want me to take it via arm-soc tree please let me
know.

Thanks,
Michal

Re: [PATCH 4/4] sdhci: arasan: Remove quirk for broken base clock

[Ulf Hansson]

On Tue, 4 Feb 2020 at 12:42, Michal Simek <michal.simek@xilinx.com> wrote:
>
> On 03. 02. 20 12:31, Adrian Hunter wrote:
> > On 21/01/20 12:21 pm, Manish Narani wrote:
> >> This patch removes quirk which indicates a broken base clock. This was
> >> making the kernel report wrong base clock of ~187MHz instead of 200MHz
> >> even as the measurement on the hardware was showing 200MHz.
> >>
> >> Signed-off-by: Manish Narani <manish.narani@xilinx.com>
> >> State: pending
> >
> > Huh?
>
> It shouldn't be here. It is internal patch labeling.
> Manish: Please send v2 with all lines you got and remove this above.

No need for a resend, I can fix this before applying, which will be
when rc1 is out.

>
> >
> > Otherwise:
> >
> > Acked-by: Adrian Hunter <adrian.hunter@intel.com>
>
> These patches requires firmware changes. Feel free to take it directly
> via your tree. If you want me to take it via arm-soc tree please let me
> know.

Thanks, I pick them up via my mmc tree then.

Kind regards
Uffe

Re: [PATCH 4/4] sdhci: arasan: Remove quirk for broken base clock

[Michal Simek]

On 04. 02. 20 13:29, Ulf Hansson wrote:
> On Tue, 4 Feb 2020 at 12:42, Michal Simek <michal.simek@xilinx.com> wrote:
>>
>> On 03. 02. 20 12:31, Adrian Hunter wrote:
>>> On 21/01/20 12:21 pm, Manish Narani wrote:
>>>> This patch removes quirk which indicates a broken base clock. This was
>>>> making the kernel report wrong base clock of ~187MHz instead of 200MHz
>>>> even as the measurement on the hardware was showing 200MHz.
>>>>
>>>> Signed-off-by: Manish Narani <manish.narani@xilinx.com>
>>>> State: pending
>>>
>>> Huh?
>>
>> It shouldn't be here. It is internal patch labeling.
>> Manish: Please send v2 with all lines you got and remove this above.
> 
> No need for a resend, I can fix this before applying, which will be
> when rc1 is out.
> 
>>
>>>
>>> Otherwise:
>>>
>>> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
>>
>> These patches requires firmware changes. Feel free to take it directly
>> via your tree. If you want me to take it via arm-soc tree please let me
>> know.
> 
> Thanks, I pick them up via my mmc tree then.

ok. Please let me know if there is any conflict. It should be simple add.

Thanks,
Michal

Re: [PATCH 0/4] Enhancements and Bug Fixes in ZynqMP SDHCI

[Ulf Hansson]

On Tue, 21 Jan 2020 at 11:21, Manish Narani <manish.narani@xilinx.com> wrote:
>
> This patch series includes:
> -> Mark the Tap Delay Node as valid for ioctl calls
> -> Add support for DLL reset in firmware driver
> -> Add support to reset DLL from Arasan SDHCI driver for ZynqMP platform
> -> Fix incorrect base clock reporting issue
>
> Manish Narani (4):
>   firmware: xilinx: Add ZynqMP Tap Delay setup ioctl to the valid list
>   firmware: xilinx: Add DLL reset support
>   mmc: sdhci-of-arasan: Add support for DLL reset for ZynqMP platforms
>   sdhci: arasan: Remove quirk for broken base clock
>
>  drivers/firmware/xilinx/zynqmp.c     |  2 +
>  drivers/mmc/host/sdhci-of-arasan.c   | 59 +++++++++++++++++++++++++++-
>  include/linux/firmware/xlnx-zynqmp.h |  9 ++++-
>  3 files changed, 68 insertions(+), 2 deletions(-)
>
> --
> 2.17.1
>

Applied for next, thanks!

Kind regards
Uffe

RE: [PATCH 0/4] Enhancements and Bug Fixes in ZynqMP SDHCI

[Manish Narani]

Hi Uffe,

> -----Original Message-----
> From: Ulf Hansson <ulf.hansson@linaro.org>
> Sent: Thursday, February 13, 2020 7:26 PM
> To: Manish Narani <MNARANI@xilinx.com>
> Cc: Michal Simek <michals@xilinx.com>; Adrian Hunter
> <adrian.hunter@intel.com>; Jolly Shah <JOLLYS@xilinx.com>; Rajan Vaja
> <RAJANV@xilinx.com>; Nava kishore Manne <navam@xilinx.com>; Tejas
> Patel <TEJASP@xilinx.com>; Linux ARM <linux-arm-
> kernel@lists.infradead.org>; Linux Kernel Mailing List <linux-
> kernel@vger.kernel.org>; linux-mmc@vger.kernel.org
> Subject: Re: [PATCH 0/4] Enhancements and Bug Fixes in ZynqMP SDHCI
> 
> On Tue, 21 Jan 2020 at 11:21, Manish Narani <manish.narani@xilinx.com>
> wrote:
> >
> > This patch series includes:
> > -> Mark the Tap Delay Node as valid for ioctl calls
> > -> Add support for DLL reset in firmware driver
> > -> Add support to reset DLL from Arasan SDHCI driver for ZynqMP platform
> > -> Fix incorrect base clock reporting issue
> >
> > Manish Narani (4):
> >   firmware: xilinx: Add ZynqMP Tap Delay setup ioctl to the valid list
> >   firmware: xilinx: Add DLL reset support
> >   mmc: sdhci-of-arasan: Add support for DLL reset for ZynqMP platforms
> >   sdhci: arasan: Remove quirk for broken base clock
> >
> >  drivers/firmware/xilinx/zynqmp.c     |  2 +
> >  drivers/mmc/host/sdhci-of-arasan.c   | 59
> +++++++++++++++++++++++++++-
> >  include/linux/firmware/xlnx-zynqmp.h |  9 ++++-
> >  3 files changed, 68 insertions(+), 2 deletions(-)
> >
> > --
> > 2.17.1
> >
> 
> Applied for next, thanks!
Thanks a lot!

- Manish