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header.from=amd.com; Received: from BYAPR12MB4758.namprd12.prod.outlook.com (2603:10b6:a03:a5::28) by DS0PR12MB6583.namprd12.prod.outlook.com (2603:10b6:8:d1::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.30; Tue, 16 May 2023 07:55:22 +0000 Received: from BYAPR12MB4758.namprd12.prod.outlook.com ([fe80::e78e:b7da:7b9a:a578]) by BYAPR12MB4758.namprd12.prod.outlook.com ([fe80::e78e:b7da:7b9a:a578%4]) with mapi id 15.20.6387.032; Tue, 16 May 2023 07:55:22 +0000 Message-ID: Date: Tue, 16 May 2023 09:54:50 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Content-Language: en-US To: Brad Larson , linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-spi@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brendan.higgins@linux.dev, briannorris@chromium.org, catalin.marinas@arm.com, conor+dt@kernel.org, davidgow@google.com, gsomlo@gmail.com, gerg@linux-m68k.org, hal.feng@starfivetech.com, hasegawa-hitomi@fujitsu.com, j.neuschaefer@gmx.net, joel@jms.id.au, kernel@esmil.dk, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, lee.jones@linaro.org, broonie@kernel.org, p.zabel@pengutronix.de, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, skhan@linuxfoundation.org, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, tonyhuang.sunplus@gmail.com, ulf.hansson@linaro.org, vaishnav.a@ti.com, walker.chen@starfivetech.com, will@kernel.org, zhuyinbo@loongson.cn, devicetree@vger.kernel.org References: <20230515181606.65953-1-blarson@amd.com> <20230515181606.65953-7-blarson@amd.com> From: Michal Simek Subject: Re: [PATCH v14 6/8] arm64: dts: Add AMD Pensando Elba SoC support In-Reply-To: <20230515181606.65953-7-blarson@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit 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List-ID: X-Mailing-List: linux-mmc@vger.kernel.org On 5/15/23 20:16, Brad Larson wrote: > Add AMD Pensando common and Elba SoC specific device nodes > > Signed-off-by: Brad Larson > --- > > v14 changes: > - Fix dtbs_check l2-cache* property issue by adding required > cache-level and cache-unified properties > - Observed the issue after updating dtschema from 2023.1 to 2023.4 > and yamllint from 1.26.3 to 1.30.0 > > v11 changes: > - Delete reset-names > - Fix spi0 compatible to be specific 'amd,pensando-elba-ctrl' > > v9 changes: > - Single node for spi0 system-controller and squash > the reset-controller child into parent > > --- > arch/arm64/boot/dts/amd/Makefile | 1 + > arch/arm64/boot/dts/amd/elba-16core.dtsi | 197 ++++++++++++++++++ > arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 80 +++++++ > arch/arm64/boot/dts/amd/elba-asic.dts | 28 +++ > arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 106 ++++++++++ > arch/arm64/boot/dts/amd/elba.dtsi | 191 +++++++++++++++++ > 6 files changed, 603 insertions(+) > create mode 100644 arch/arm64/boot/dts/amd/elba-16core.dtsi > create mode 100644 arch/arm64/boot/dts/amd/elba-asic-common.dtsi > create mode 100644 arch/arm64/boot/dts/amd/elba-asic.dts > create mode 100644 arch/arm64/boot/dts/amd/elba-flash-parts.dtsi > create mode 100644 arch/arm64/boot/dts/amd/elba.dtsi > > diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile > index 68103a8b0ef5..8502cc2afbc5 100644 > --- a/arch/arm64/boot/dts/amd/Makefile > +++ b/arch/arm64/boot/dts/amd/Makefile > @@ -1,2 +1,3 @@ > # SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_ARCH_PENSANDO) += elba-asic.dtb > dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb > diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts/amd/elba-16core.dtsi > new file mode 100644 > index 000000000000..f9f9f5fd5f69 > --- /dev/null > +++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi > @@ -0,0 +1,197 @@ > +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) > +/* > + * Copyright 2020-2022 Advanced Micro Devices, Inc. 2023 and the same below. > + */ > + > +/ { > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { cpu = <&cpu0>; }; > + core1 { cpu = <&cpu1>; }; > + core2 { cpu = <&cpu2>; }; > + core3 { cpu = <&cpu3>; }; > + }; > + > + cluster1 { > + core0 { cpu = <&cpu4>; }; > + core1 { cpu = <&cpu5>; }; > + core2 { cpu = <&cpu6>; }; > + core3 { cpu = <&cpu7>; }; > + }; > + > + cluster2 { > + core0 { cpu = <&cpu8>; }; > + core1 { cpu = <&cpu9>; }; > + core2 { cpu = <&cpu10>; }; > + core3 { cpu = <&cpu11>; }; > + }; > + > + cluster3 { > + core0 { cpu = <&cpu12>; }; > + core1 { cpu = <&cpu13>; }; > + core2 { cpu = <&cpu14>; }; > + core3 { cpu = <&cpu15>; }; > + }; > + }; > + > + /* CLUSTER 0 */ > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x0>; Do you really need 2/0 split here. The first cell is 0 anyway. > + next-level-cache = <&l2_0>; > + enable-method = "psci"; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x1>; > + next-level-cache = <&l2_0>; > + enable-method = "psci"; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x2>; > + next-level-cache = <&l2_0>; > + enable-method = "psci"; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x3>; > + next-level-cache = <&l2_0>; > + enable-method = "psci"; > + }; > + > + l2_0: l2-cache0 { > + compatible = "cache"; > + cache-unified; > + cache-level = <2>; > + }; > + > + /* CLUSTER 1 */ > + cpu4: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x100>; > + next-level-cache = <&l2_1>; > + enable-method = "psci"; > + }; > + > + cpu5: cpu@101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x101>; > + next-level-cache = <&l2_1>; > + enable-method = "psci"; > + }; > + > + cpu6: cpu@102 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x102>; > + next-level-cache = <&l2_1>; > + enable-method = "psci"; > + }; > + > + cpu7: cpu@103 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x103>; > + next-level-cache = <&l2_1>; > + enable-method = "psci"; > + }; > + > + l2_1: l2-cache1 { > + compatible = "cache"; > + cache-unified; > + cache-level = <2>; > + }; > + > + /* CLUSTER 2 */ > + cpu8: cpu@200 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x200>; > + next-level-cache = <&l2_2>; > + enable-method = "psci"; > + }; > + > + cpu9: cpu@201 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x201>; > + next-level-cache = <&l2_2>; > + enable-method = "psci"; > + }; > + > + cpu10: cpu@202 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x202>; > + next-level-cache = <&l2_2>; > + enable-method = "psci"; > + }; > + > + cpu11: cpu@203 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x203>; > + next-level-cache = <&l2_2>; > + enable-method = "psci"; > + }; > + > + l2_2: l2-cache2 { > + compatible = "cache"; > + cache-unified; > + cache-level = <2>; > + }; > + > + /* CLUSTER 3 */ > + cpu12: cpu@300 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x300>; > + next-level-cache = <&l2_3>; > + enable-method = "psci"; > + }; > + > + cpu13: cpu@301 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x301>; > + next-level-cache = <&l2_3>; > + enable-method = "psci"; > + }; > + > + cpu14: cpu@302 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x302>; > + next-level-cache = <&l2_3>; > + enable-method = "psci"; > + }; > + > + cpu15: cpu@303 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x303>; > + next-level-cache = <&l2_3>; > + enable-method = "psci"; > + }; > + > + l2_3: l2-cache3 { > + compatible = "cache"; > + cache-unified; > + cache-level = <2>; > + }; > + }; > +}; > diff --git a/arch/arm64/boot/dts/amd/elba-asic-common.dtsi b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi > new file mode 100644 > index 000000000000..1a615788f54e > --- /dev/null > +++ b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi > @@ -0,0 +1,80 @@ > +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) > +/* > + * Copyright 2020-2022 Advanced Micro Devices, Inc. > + */ > + > +&ahb_clk { > + clock-frequency = <400000000>; > +}; > + > +&emmc_clk { > + clock-frequency = <200000000>; > +}; > + > +&flash_clk { > + clock-frequency = <400000000>; > +}; > + > +&ref_clk { > + clock-frequency = <156250000>; > +}; > + > +&qspi { > + status = "okay"; > + > + flash0: flash@0 { > + compatible = "jedec,spi-nor"; > + reg = <0>; > + spi-max-frequency = <40000000>; > + spi-rx-bus-width = <2>; > + m25p,fast-read; > + cdns,read-delay = <0>; > + cdns,tshsl-ns = <0>; > + cdns,tsd2d-ns = <0>; > + cdns,tchsh-ns = <0>; > + cdns,tslch-ns = <0>; > + }; > +}; > + > +&gpio0 { > + status = "okay"; > +}; > + > +&emmc { > + bus-width = <8>; > + cap-mmc-hw-reset; > + resets = <&rstc 0>; > + status = "okay"; > +}; > + > +&wdt0 { > + status = "okay"; > +}; > + > +&i2c0 { > + clock-frequency = <100000>; > + status = "okay"; > + > + rtc@51 { > + compatible = "nxp,pcf85263"; > + reg = <0x51>; > + }; > +}; > + > +&spi0 { > + #address-cells = <1>; > + #size-cells = <0>; > + num-cs = <4>; > + cs-gpios = <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>, > + <&porta 7 GPIO_ACTIVE_LOW>; > + status = "okay"; > + > + rstc: system-controller@0 { > + compatible = "amd,pensando-elba-ctrl"; > + reg = <0>; > + spi-max-frequency = <12000000>; > + interrupt-parent = <&porta>; > + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; > + #reset-cells = <1>; > + }; > +}; > diff --git a/arch/arm64/boot/dts/amd/elba-asic.dts b/arch/arm64/boot/dts/amd/elba-asic.dts > new file mode 100644 > index 000000000000..c3f4da2f7449 > --- /dev/null > +++ b/arch/arm64/boot/dts/amd/elba-asic.dts > @@ -0,0 +1,28 @@ > +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) > +/* > + * Device Tree file for AMD Pensando Elba Board. > + * > + * Copyright 2020-2022 Advanced Micro Devices, Inc. > + */ > + > +/dts-v1/; > + > +#include "elba.dtsi" > +#include "elba-16core.dtsi" > +#include "elba-asic-common.dtsi" > +#include "elba-flash-parts.dtsi" > + > +/ { > + model = "AMD Pensando Elba Board"; > + compatible = "amd,pensando-elba-ortano", "amd,pensando-elba"; > + > + aliases { > + serial0 = &uart0; > + spi0 = &spi0; > + spi1 = &qspi; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > diff --git a/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi > new file mode 100644 > index 000000000000..734893fef2c3 > --- /dev/null > +++ b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi > @@ -0,0 +1,106 @@ > +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) > +/* > + * Copyright 2020-2022 Advanced Micro Devices, Inc. > + */ > + > +&flash0 { > + partitions { > + compatible = "fixed-partitions"; > + #address-cells = <1>; > + #size-cells = <1>; > + partition@0 { > + label = "flash"; > + reg = <0x10000 0xfff0000>; This doesn't fit with partition@0 above. Also size is weird. > + }; > + > + partition@f0000 { > + label = "golduenv"; > + reg = <0xf0000 0x10000>; > + }; > + > + partition@100000 { > + label = "boot0"; > + reg = <0x100000 0x80000>; > + }; > + > + partition@180000 { > + label = "golduboot"; > + reg = <0x180000 0x200000>; > + }; > + > + partition@380000 { > + label = "brdcfg0"; > + reg = <0x380000 0x10000>; > + }; > + > + partition@390000 { > + label = "brdcfg1"; > + reg = <0x390000 0x10000>; > + }; > + > + partition@400000 { > + label = "goldfw"; > + reg = <0x400000 0x3c00000>; This size looks weird. > + }; > + > + partition@4010000 { > + label = "fwmap"; > + reg = <0x4010000 0x20000>; > + }; > + > + partition@4030000 { > + label = "fwsel"; > + reg = <0x4030000 0x20000>; > + }; > + > + partition@4090000 { > + label = "bootlog"; > + reg = <0x4090000 0x20000>; > + }; > + > + partition@40b0000 { > + label = "panicbuf"; > + reg = <0x40b0000 0x20000>; > + }; > + > + partition@40d0000 { > + label = "uservars"; > + reg = <0x40d0000 0x20000>; > + }; > + > + partition@4200000 { > + label = "uboota"; > + reg = <0x4200000 0x400000>; > + }; > + > + partition@4600000 { > + label = "ubootb"; > + reg = <0x4600000 0x400000>; > + }; > + > + partition@4a00000 { > + label = "mainfwa"; > + reg = <0x4a00000 0x1000000>; > + }; > + > + partition@5a00000 { > + label = "mainfwb"; > + reg = <0x5a00000 0x1000000>; > + }; > + > + partition@6a00000 { > + label = "diaguboot"; > + reg = <0x6a00000 0x400000>; > + }; > + here is gap > + partition@8000000 { > + label = "diagfw"; > + reg = <0x8000000 0x7fe0000>; > + }; > + > + partition@ffe0000 { > + label = "ubootenv"; > + reg = <0xffe0000 0x10000>; > + }; And this is missing space description. Thanks, Michal