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From: John Garry <john.garry@huawei.com>
To: <Tudor.Ambarus@microchip.com>, <linux-mtd@lists.infradead.org>
Cc: broonie@kernel.org, chenxiang66@hisilicon.com
Subject: Re: flash_lock issue for n25q 128mb spi nor part
Date: Tue, 3 Dec 2019 12:35:10 +0000
Message-ID: <00cf6eab-9798-b0e9-e4a2-5b2f8374b698@huawei.com> (raw)
In-Reply-To: <ce595e1f-a703-e1f1-264b-6c7e66dcc1fa@microchip.com>

On 03/12/2019 12:27, Tudor.Ambarus@microchip.com wrote:
> 
> 
> On 12/3/19 2:05 PM, Tudor.Ambarus@microchip.com wrote:
>> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
>> index f4afe123e9dc..f1490c7b5cb9 100644
>> --- a/drivers/mtd/spi-nor/spi-nor.c
>> +++ b/drivers/mtd/spi-nor/spi-nor.c
>> @@ -1033,10 +1033,19 @@ static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)
>>
>>          sr_cr[0] = sr1;
>>
>> +       dev_err(nor->dev, "before write: sr_cr[0] = %02x, sr_cr[1] = %02x\n",
>> +               sr_cr[0], sr_cr[1]);
>> +
>>          ret = spi_nor_write_sr(nor, sr_cr, 2);
>>          if (ret)
>>                  return ret;
>>
>> +       ret = spi_nor_read_sr(nor, &sr_cr[0]);
>> +       if (ret)
>> +               return ret;
>> +
>> +       dev_err(nor->dev, "read back sr1: sr_cr[0] = %02x\n", sr_cr[0]);
>> +
>>          if (nor->flags & SNOR_F_NO_READ_CR)
>>                  return 0;
>>
>> @@ -1046,6 +1055,8 @@ static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)
>>          if (ret)
>>                  return ret;
>>
>> +       dev_err(nor->dev, "read back sr2: sr_cr[1] = %02x\n", sr_cr[1]);
>> +
>>          if (cr_written != sr_cr[1]) {
>>                  dev_dbg(nor->dev, "CR: read back test failed\
> 
> On n25q256a I obtain:
> 
> root@sama5d2-xplained-sd:~# flash_lock -l /dev/mtd1
> spi-nor spi1.0: before write: sr_cr[0] = 9e, sr_cr[1] = ff
> spi-nor spi1.0: read back sr1: sr_cr[0] = 02
> spi-nor spi1.0: read back sr2: sr_cr[1] = ff
> 

So here is what I get:

root@ubuntu:/home/john# flash_lock -l /dev/mtd0
[  109.037492] spi-nor spi-PRP0001:00: before write: sr_cr[0] = 9e, 
sr_cr[1] = 00
[  109.044769] spi-nor spi-PRP0001:00: read back sr1: sr_cr[0] = 02
[  109.050790] spi-nor spi-PRP0001:00: read back sr2: sr_cr[1] = 00


> the 16 bit write SR does not execute correctly and the WE remains set. If
> neither of the micron flashes do not support the 16 bit write SR, we can add a
> condition based on MFR. Let me check few datasheets.
> 

OK, thanks.

John


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Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-02 17:28 John Garry
2019-12-03  9:45 ` Tudor.Ambarus
2019-12-03 10:31   ` John Garry
2019-12-03 11:07     ` Tudor.Ambarus
2019-12-03 11:44       ` John Garry
2019-12-03 12:05         ` Tudor.Ambarus
2019-12-03 12:27           ` Tudor.Ambarus
2019-12-03 12:35             ` John Garry [this message]
2019-12-03 13:57               ` John Garry
2019-12-03 14:44                 ` Tudor.Ambarus
2019-12-03 15:29                   ` John Garry
2019-12-04 11:10                     ` John Garry
2019-12-16 18:09                       ` Tudor.Ambarus
2019-12-17  8:57                         ` Vignesh Raghavendra
2019-12-17 10:09                           ` John Garry
2020-01-09 10:36                           ` John Garry
2020-01-10 11:51                             ` Tudor.Ambarus
2020-01-10 11:56                               ` John Garry
2020-01-15  9:28                                 ` John Garry
2019-12-03 14:16               ` [PATCH] mtd: spi-nor: Fix the write Status Register on micron flashes Tudor.Ambarus
2019-12-03 14:50                 ` [PATCH v2] mtd: spi-nor: Fix the writing of the " Tudor.Ambarus
2019-12-04 10:18                   ` John Garry
2020-01-09 19:14                   ` Miquel Raynal

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