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Wed, 22 Jan 2020 20:42:00 +0900 (KST) Received: from ara-VirtualBox (unknown [10.88.100.192]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20200122114200epsmtip1acb49c6f2e25debacb128b28e4644829~sMrSp3Fi43183231832epsmtip1C; Wed, 22 Jan 2020 11:42:00 +0000 (GMT) Message-ID: <0a2c4e9132f7d4f61fd3ce87c5393c65515b937e.camel@samsung.com> Subject: Re: [PATCH v3 2/3] mtd: spi-nor: add 4bit block protection support From: Jungseung Lee To: Jungseung Lee , Tudor.Ambarus@microchip.com, js07.lee@samsung.com Date: Wed, 22 Jan 2020 20:42:00 +0900 In-Reply-To: X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.1 Mime-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Se0hTYRjG+3Z2dqPFaaa9aOA6paSkbq6tJRmBK2YmKCVZgeugh03ajZ1p GUFNKsrStAhxGkl5QS0XU3JaYSilVlaolFqBmeuGSkWpIFbbjqH//b73fZ73+W4CTFLMCxXk mu20zUwZSZ6Ie687KjZGqNyUJXOXhqsXqqY56vGReVx9v7COr/5Rs1P9t/87fyeubXe+52tb ak5p383VIm1JayPS9gy3cdLwQ8btBprKoW1S2pxtyck16xPJlH26JJ1SJZPHyLept5JSM2Wi E0nN3rSY3blGXzYpzaeMeb5SGsUwZNyO7TZLnp2WGiyMPZGkrTlGq1xmjWUoE5Nn1sdmW0wJ cpksXulTHjEaHM2duLUq/Pis9xZ+GjWGFCGhAIgt8L6lAytCIoGE8CDocTlwdvETwdAf72Jn BkHH3WLOf8tCQ+ei6iGCTwNDfHYxiaCv9gHXrxITWhi5divgCCJSoLJkiudnHhENw/Nu3M9r iMPgvTIaqGNEPLx79oHvZy4RAbcvNCI/C4l0uNEyyWOTN8PU0xLffIFv/mpY8ASx1nBom6oK 7BSIRzx4fH4M82uA0EB9r461BsG3nlY+y6Hw9fK5RWagvaGMz3rPIBivr1lsKGB66k5gDkZE gasjji2vh/b564jNXQXTvy/hbJQYzp+TsBISJsfOcFkGePWxGGdZC3MTngBLCBcHXNczS5HU uXQY57LDOJdyqxHWiEJoK2PS04zcGr/8fd0o8BWjVR5088XeLkQIELlSbPBGZklwKp8pMHUh EGDkGnF1YUSWRJxDFZygbRadLc9IM11I6bvqMiw0ONvi+9hmu06ujFcoFOotqq0qpYJcKy7X SLMkhJ6y00dp2krb/vs4AmHoadQp6ui+LKr7dPJR7GQY5k6MbFsxOPokeMTxMjldGZm+392S mvmmOqG2qFTz2b1u18TESUP3rLYwKTmjYcCxR7OR6sl/PePIrnjedPDtgVSJpwzbICxKFZ/t bz7WG9abUe/qu2p9wJFWGTJ/fblYcbP2Y2V50yXmT0rSWaeBO1j3hOQyBkoejdkY6h+forz0 oAMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrPLMWRmVeSWpSXmKPExsWy7bCSnC6HqUacwdVF5hZ/57xjsnh08zer xe6mZewWH5c4WPw/+4HdgdVj56y77B6bl9R73PmxlNGjb8sqRo/jN7YzBbBGcdmkpOZklqUW 6dslcGU0rtvPWjBHvuL708WsDYyrxLoYOTkkBEwk/q7cz9rFyMUhJLCbUWL+ZxAHJCEh8Wjn F5YuRg4gW1ji8OFiiJpXjBJ7ts9lB6nhFfCQuDl1MROILSzgLTG77y0biM0moCVx4/cmsDki AjES33/eBqtnFjCSuHP6IZjNIqAqsaZzFSOIzSkQKDF/8xs2iAWbmSTOTN7PBNGgKdG6/Tc7 xEE6Em9P9YEdxCsgKPF3hzBEibzE9rdzmCcwCs5C0jELoWoWkqoFjMyrGCVTC4pz03OLDQuM 8lLL9YoTc4tL89L1kvNzNzGCg11LawfjiRPxhxgFOBiVeHgznqrFCbEmlhVX5h5ilOBgVhLh XdCkGifEm5JYWZValB9fVJqTWnyIUZqDRUmcVz7/WKSQQHpiSWp2ampBahFMlomDU6qBMeif 3Er5t4vZZvxW/uMlUbs118pwI784RyznSxZlRoHDG9ZI2zP7CV2S9dvdoeCepNj00VKz+zbf GrZsw++pG+vKGmXrJ7hyTdqhtGrZ80zTk+tcrQ/c121wXWaikcmveWJa23Ke0xmrpgQdC77F OYvza82HdiOePO5jD+S7etuWyep9CpulxFKckWioxVxUnAgAkYunKHICAAA= X-CMS-MailID: 20200122114200epcas1p499bec859ec168fb69b1a11c5272a1dcc X-Msg-Generator: CA X-Sendblock-Type: SVC_REQ_APPROVE CMS-TYPE: 101P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20200113055910epcas1p377b2618bea2ca860acac2b6f34e2b83e References: <20200113055907.9029-1-js07.lee@samsung.com> <20200113055907.9029-2-js07.lee@samsung.com> <3703036.Ns4Yp6NO8s@localhost.localdomain> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200122_034207_640512_6F8454C1 X-CRM114-Status: GOOD ( 33.78 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-mtd@lists.infradead.org, vigneshr@ti.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org Hi, Tudor, 2020-01-18 (Sat), 00:06 +0900, Jungseung Lee: > Hi, Tudor, > > On Tue, Jan 14, 2020 at 7:49 PM wrote: > > > > Hi, Jungseung, > > > > Thanks for working on this. > > > > On Monday, January 13, 2020 7:59:06 AM EET Jungseung Lee wrote: > > > EXTERNAL EMAIL: Do not click links or open attachments unless you > > > know the > > > content is safe > > > > > > Currently, we are supporting block protection only for > > > flash chips with 3 block protection bits in the SR register. > > > This patch enables block protection support for some flash with > > > 4 block protection bits(bp0-3). > > > > Some? Isn't this generic for all the flashes that support BP0-3? > > > > This one would be a generic solution to support BP0-3 on Status > Register. > From my study, this covers all the flashes listed on spi-nor.c that > have BP0-3 bit on SR. > It looks like I have to change this description. > > Note that it is NOT for some flashes that have BP0-3 in another > register. > As you know, just like SPI_NOR_HAS_TB did. > > > > > > > Signed-off-by: Jungseung Lee > > > --- > > > v3 : > > > Fix wrong ofs calculation on v2 patch > > > v2 : > > > Add sample table portion about 4bit block protection on the > > > comment > > > Trivial coding style change > > > > > > drivers/mtd/spi-nor/spi-nor.c | 127 > > > +++++++++++++++++++++++++++++----- > > > include/linux/mtd/spi-nor.h | 8 +++ > > > 2 files changed, 119 insertions(+), 16 deletions(-) > > > > > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi- > > > nor/spi-nor.c > > > index e3da6a8654a8..7e8af6c4fdfa 100644 > > > --- a/drivers/mtd/spi-nor/spi-nor.c > > > +++ b/drivers/mtd/spi-nor/spi-nor.c > > > @@ -238,6 +238,14 @@ struct flash_info { > > > * status register. Must > > > be used > > > with * SPI_NOR_HAS_TB. > > > */ > > > +#define SPI_NOR_HAS_BP3 BIT(17) /* > > > + * Flash SR has 4 bit > > > fields (BP0-3) > > > + * for block protection. > > > + */ > > > +#define SPI_NOR_BP3_SR_BIT6 BIT(18) /* > > > + * BP3 is bit 6 of status > > > register. > > > + * Must be used with > > > > Are we safe to replace SPI_NOR_TB_SR_BIT6 and SPI_NOR_BP3_SR_BIT6 > > with a > > SPI_NOR_SR_TB_BIT6_BP3_BIT5? Or maybe with a > > SPI_NOR_SR_BP3_BIT6_TB_BIT5, how > > is more convenient? > > > > Let's think about some flash in which BP0-3 exists in the status > register but TB exists in another register. > for example, mx25u12835f. > I haven't tested yet, but according to the datasheet, I think this > patch can support 4bit block protection for the flash. > > In order to embrace the case, how about letting them as It is. > Is there any suggestion? > Hmm.. I again have summarized the case of using 4bit block protection. * Not supporting TB on status register. - BP3(BIT5) SPI_NOR_HAS_BP3 - BP3(BIT6) SPI_NOR_HAS_BP3 | SPI_NOR_BP3_SR_BIT6 * Supporting TB on status register. - TB(BIT6), BP3(BIT5) SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_HAS_BP3 vs SPI_NOR_HAS_TB | SPI_NOR_HAS_BP3 | SPI_NOR_SR_TB_BIT6_BP3_BIT5 - TB(BIT5), BP3(BIT6) SPI_NOR_HAS_TB | SPI_NOR_HAS_BP3 | SPI_NOR_BP3_SR_BIT6 vs SPI_NOR_HAS_TB | SPI_NOR_HAS_BP3 | SPI_NOR_SR_TB_BIT5_BP3_BIT6 SPI_NOR_BP3_SR_BIT6 and SPI_NOR_TB_SR_BIT6 must exist becuase it maybe used. It would be ok to add some definitions(as you mentioned) to get same value with SPI_NOR_BP3_SR_BIT6 or SPI_NOR_TB_SR_BIT6 for readabilty. But I think there is nothing looks so cool. Any suggestion? > > Cheers, > > ta > > > > Thanks, Jungseung Lee ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/