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[118.238.38.77]) by smtp.gmail.com with ESMTPSA id v8-20020a17090a778800b001cd4989ff3fsm2592576pjk.6.2022.05.04.00.59.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 May 2022 00:59:51 -0700 (PDT) Message-ID: <0d2d0001-78f8-32d1-78eb-0559f8865363@gmail.com> Date: Wed, 4 May 2022 16:59:48 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.8.1 Subject: Re: [PATCH v14 8/8] mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups Content-Language: en-US To: Tudor.Ambarus@microchip.com, p.yadav@ti.com, michael@walle.cc Cc: miquel.raynal@bootlin.com, richard@nod.at, Bacem.Daassi@infineon.com, Takahiro.Kuwano@infineon.com, linux-mtd@lists.infradead.org References: <20220503081627.341870-1-tudor.ambarus@microchip.com> <20220503081627.341870-9-tudor.ambarus@microchip.com> <6b343fd7-96f9-b2de-8eb3-196ddf91b93c@gmail.com> <39161526-fc95-63fc-8b43-83c2e539ae36@microchip.com> From: Takahiro Kuwano In-Reply-To: <39161526-fc95-63fc-8b43-83c2e539ae36@microchip.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220504_005953_949518_410BC91D X-CRM114-Status: GOOD ( 16.90 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org On 5/4/2022 4:47 PM, Tudor.Ambarus@microchip.com wrote: > On 5/4/22 10:38, Takahiro Kuwano wrote: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >> >> Hi Tudor, > > Hi! > >> >> On 5/3/2022 5:16 PM, Tudor Ambarus wrote: >>> From: Takahiro Kuwano >>> >>> The S25HL-T/S25HS-T family is the Infineon SEMPER Flash with Quad SPI. >>> >>> These Infineon chips support volatile version of configuration registers >>> and it is recommended to update volatile registers in the field application >>> due to a risk of the non-volatile registers corruption by power interrupt. >>> Add support for volatile QE bit. >>> >>> For the single-die package parts (512Mb and 1Gb), only bottom 4KB and >>> uniform sector sizes are supported. This is due to missing or incorrect >>> entries in SMPT. Fixup for other sector sizes configurations will be >>> followed up as needed. >>> >>> Tested on Xilinx Zynq-7000 FPGA board. >>> >>> Signed-off-by: Takahiro Kuwano >>> Reviewed-by: Tudor Ambarus >>> --- >>> drivers/mtd/spi-nor/spansion.c | 125 +++++++++++++++++++++++++++++++++ >>> 1 file changed, 125 insertions(+) >>> >>> diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c >>> index e130f5398763..f78a15b985ea 100644 >>> --- a/drivers/mtd/spi-nor/spansion.c >>> +++ b/drivers/mtd/spi-nor/spansion.c >>> @@ -14,6 +14,8 @@ >>> #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ >>> #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ >>> #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ >>> +#define SPINOR_REG_CYPRESS_CFR1V 0x00800002 >>> +#define SPINOR_REG_CYPRESS_CFR1V_QUAD_EN BIT(1) /* Quad Enable */ >>> #define SPINOR_REG_CYPRESS_CFR2V 0x00800003 >>> #define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24 0xb >>> #define SPINOR_REG_CYPRESS_CFR3V 0x00800004 >>> @@ -113,6 +115,63 @@ static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) >>> return 0; >>> } >>> >>> +/** >>> + * cypress_nor_quad_enable_volatile() - enable Quad I/O mode in volatile >>> + * register. >>> + * @nor: pointer to a 'struct spi_nor' >>> + * >>> + * It is recommended to update volatile registers in the field application due >>> + * to a risk of the non-volatile registers corruption by power interrupt. This >>> + * function sets Quad Enable bit in CFR1 volatile. If users set the Quad Enable >>> + * bit in the CFR1 non-volatile in advance (typically by a Flash programmer >>> + * before mounting Flash on PCB), the Quad Enable bit in the CFR1 volatile is >>> + * also set during Flash power-up. >>> + * >>> + * Return: 0 on success, -errno otherwise. >>> + */ >>> +static int cypress_nor_quad_enable_volatile(struct spi_nor *nor) >>> +{ >>> + struct spi_mem_op op; >>> + u8 cfr1v_written; >>> + int ret; >>> + >>> + op = (struct spi_mem_op) >>> + CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_nbytes, >>> + SPINOR_REG_CYPRESS_CFR1V, >>> + nor->bouncebuf); >>> + >> The following lines are missing. >> >> ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); >> if (ret) >> return ret; > > Sorry, I'll add them in the next version, seems that I handled the conflicts > badly :). Does it work with the read? Have you tested the patch set? > No problem. Yes, I tested and it's working. Thanks again, Takahiro ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/