From: <Tudor.Ambarus@microchip.com>
To: <michael@walle.cc>
Cc: vigneshr@ti.com, richard@nod.at, linux-kernel@vger.kernel.org,
linux-mtd@lists.infradead.org, miquel.raynal@bootlin.com,
linux-arm-kernel@lists.infradead.org
Subject: Re: [RFC PATCH 1/2] mtd: spi-nor: atmel: remove global SNOR_F_HAS_LOCK
Date: Thu, 1 Oct 2020 14:25:43 +0000 [thread overview]
Message-ID: <137692b0-ab6d-b9be-17c2-68e3b3146076@microchip.com> (raw)
In-Reply-To: <871da0d058ba89320615098ee26150b3@walle.cc>
On 10/1/20 5:12 PM, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Am 2020-10-01 16:06, schrieb Tudor.Ambarus@microchip.com:
>> On 10/1/20 3:28 PM, Michael Walle wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know
>>> the content is safe
>>>
>>> This is considered bad for the following reasons:
>>> (1) We only support the block protection with BPn bits for write
>>> protection. Not all Atmel parts support this.
>>> (2) Newly added flash chip will automatically inherit the "has
>>> locking" support and thus needs to explicitly tested. Better
>>> be opt-in instead of opt-out.
>>> (3) There are already supported flashes which don't support the
>>> locking
>>> scheme. So I assume this wasn't properly tested before adding
>>> that
>>> chip; which enforces my previous argument that locking
>>> support should
>>> be an opt-in.
>>>
>>> Remove the global flag and add individual flags to all flashes
>>> which supports BP locking. In particular the following flashes
>>> don't support the BP scheme:
>>> - AT26F004
>>> - AT25SL321
>>> - AT45DB081D
>>>
>>> Signed-off-by: Michael Walle <michael@walle.cc>
>>> ---
>>> drivers/mtd/spi-nor/atmel.c | 28 +++++++++-------------------
>>> 1 file changed, 9 insertions(+), 19 deletions(-)
>>>
>>> diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c
>>> index 3f5f21a473a6..49d392c6c8bc 100644
>>> --- a/drivers/mtd/spi-nor/atmel.c
>>> +++ b/drivers/mtd/spi-nor/atmel.c
>>> @@ -10,37 +10,27 @@
>>>
>>> static const struct flash_info atmel_parts[] = {
>>> /* Atmel -- some are (confusingly) marketed as "DataFlash" */
>>> - { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
>>> - { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
>>> + { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K |
>>> SPI_NOR_HAS_LOCK) },
>>> + { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K |
>>> SPI_NOR_HAS_LOCK) },
>>
>> after a quick look in the datasheets of these flashes, I suspect that
>> what we have now in the SPI NOR core for SR locking does not work for
>> them. They probably supported just "unlock all", clearing all the
>> BP bits. Anyway, different problem.
>>>
>>> - { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
>>> - { "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
>>> - { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
>>> - { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
>>> + { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K |
>>> SPI_NOR_HAS_LOCK) },
>>
>> this one does not support BP locking:
>> https://www.adestotech.com/wp-content/uploads/doc3668.pdf
>>
>>> + { "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K |
>>> SPI_NOR_HAS_LOCK) },
>>
>> neither this one:
>> https://datasheet.octopart.com/AT25DF321-S3U-Atmel-datasheet-8700896.pdf
>>
>>> + { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K |
>>> SPI_NOR_HAS_LOCK) },
>>
>> nor this one: https://www.adestotech.com/wp-content/uploads/doc3686.pdf
>>
>>> + { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K |
>>> SPI_NOR_HAS_LOCK) },
>>
>> nor this one: https://www.adestotech.com/wp-content/uploads/doc3680.pdf
>>
>> I stop here.
>
> These are all the ones which use the global unlock. I cannot just skip
> the HAS_LOCK bit here, because otherwise this patch wouldn't be
> backwards
> compatibe. Yes I missed that in the commit log, my bad.
>
No worries.
"unlock all at boot" just cleared the SR bits. Clearing the SR bits unlocks
these flashes?
Cheers,
ta
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2020-10-01 14:26 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-01 12:28 [RFC PATCH 1/2] mtd: spi-nor: atmel: remove global SNOR_F_HAS_LOCK Michael Walle
2020-10-01 12:28 ` [RFC PATCH 2/2] mtd: spi-nor: sst: " Michael Walle
2020-10-01 13:21 ` [RFC PATCH 1/2] mtd: spi-nor: atmel: " Tudor.Ambarus
2020-10-01 14:06 ` Tudor.Ambarus
2020-10-01 14:12 ` Michael Walle
2020-10-01 14:25 ` Tudor.Ambarus [this message]
2020-10-01 14:37 ` Michael Walle
2020-10-01 15:25 ` Tudor.Ambarus
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=137692b0-ab6d-b9be-17c2-68e3b3146076@microchip.com \
--to=tudor.ambarus@microchip.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mtd@lists.infradead.org \
--cc=michael@walle.cc \
--cc=miquel.raynal@bootlin.com \
--cc=richard@nod.at \
--cc=vigneshr@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).