From: Piotr Sroka <piotrs@cadence.com>
To: <linux-kernel@vger.kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org,
Boris Brezillon <bbrezillon@kernel.org>,
Richard Weinberger <richard@nod.at>,
Marek Vasut <marek.vasut@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
linux-mtd@lists.infradead.org,
BrianNorris <computersforpeace@gmail.com>,
David Woodhouse <dwmw2@infradead.org>,
Piotr Sroka <piotrs@cadence.com>
Subject: [PATCH 2/2] dt-bindings: nand: Add Cadence NAND controller driver
Date: Tue, 29 Jan 2019 16:10:40 +0000 [thread overview]
Message-ID: <20190129161040.20299-1-piotrs@cadence.com> (raw)
In-Reply-To: <20190129160337.24350-1-piotrs@cadence.com>
Signed-off-by: Piotr Sroka <piotrs@cadence.com>
---
.../devicetree/bindings/mtd/cadence-nand.txt | 35 ++++++++++++++++++++++
1 file changed, 35 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/cadence-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd/cadence-nand.txt b/Documentation/devicetree/bindings/mtd/cadence-nand.txt
new file mode 100644
index 000000000000..82afa34d5652
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/cadence-nand.txt
@@ -0,0 +1,35 @@
+* Cadence NAND controller
+
+Required properties:
+ - compatible : "cdns,hpnfc-nand"
+ - reg : Contains two entries, each of which is a tuple consisting of a
+ physical address and length. The first entry is the address and
+ length of the controller register set. The second entry is the
+ address and length of the Slave DMA data port.
+ - interrupts : The interrupt number.
+ - clocks: phandle of the controller core clock (nf_clk).
+
+Optional properties:
+Driver calculates controller timings base on NAND flash memory timings and
+the following delays in picoseconds.
+ - cdns,if-skew : Skew value of the output signals of the NAND Flash interface
+ - cdns,nand2-delay : Delay value of one NAND2 gate from which
+ the delay element is build
+ - cdns,board-delay : Estimated Board delay. The value includes the total
+ round trip delay for the signals and is used for deciding on values
+ associated with data read capture. The example formula for SDR mode is
+ the following:
+ board_delay = RE#PAD_delay + PCB trace to device + PCB trace from device
+ + DQ PAD delay
+
+Example
+
+nand: nand@60000000 {
+ compatible = "cdns,hpnfc-nand";
+ reg = <0x60000000 0x10000>, <0x80000000 0x10000>;
+ clocks = <&nf_clk>;
+ cdns,if-skew = <50>;
+ cdns,nand2-delay = <37>;
+ cdns,board-delay = <4830>;
+ interrupts = <2 0>;
+};
--
2.15.0
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next prev parent reply other threads:[~2019-01-29 16:11 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-29 16:03 [PATCH 0/2] mtd: nand: Add Cadence NAND controller driver Piotr Sroka
2019-01-29 16:07 ` [PATCH 1/2] " Piotr Sroka
2019-01-29 18:19 ` Boris Brezillon
2019-02-07 13:20 ` Piotr Sroka
2019-01-29 16:10 ` Piotr Sroka [this message]
2019-01-29 17:21 ` [PATCH 2/2] dt-bindings: " Boris Brezillon
2019-02-05 17:08 ` Piotr Sroka
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