Hi Maxime,

Maxime Ripard <maxime.ripard@bootlin.com> wrote on Fri, 5 Apr 2019
11:16:07 +0200:

> On Thu, Apr 04, 2019 at 06:21:10PM +0200, Miquel Raynal wrote:
> > Allwinner NAND controllers can make use of DMA to enhance the I/O
> > throughput thanks to ECC pipelining. DMA handling with sun8i NAND IP
> > is a bit different than with the older SoCs, hence the introduction of
> > a new compatible to handle:
> > * the differences between register offsets,
> > * the burst length change from 4 to minimum 8,
> > * drive SRAM accesses through the AHB bus instead of the MBUS.
> >
> > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> > ---
> >  drivers/mtd/nand/raw/sunxi_nand.c | 75 ++++++++++++++++++++++++++++---
> >  1 file changed, 68 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c
> > index 4282bc477761..49cd5067adaa 100644
> > --- a/drivers/mtd/nand/raw/sunxi_nand.c
> > +++ b/drivers/mtd/nand/raw/sunxi_nand.c
> > @@ -42,7 +42,8 @@
> >  #define NFC_REG_CMD		0x0024
> >  #define NFC_REG_RCMD_SET	0x0028
> >  #define NFC_REG_WCMD_SET	0x002C
> > -#define NFC_REG_IO_DATA		0x0030
> > +#define NFC_REG_A10_IO_DATA	0x0030
> > +#define NFC_REG_A33_IO_DATA	0x0300
> >  #define NFC_REG_ECC_CTL		0x0034
> >  #define NFC_REG_ECC_ST		0x0038
> >  #define NFC_REG_DEBUG		0x003C
> > @@ -200,6 +201,22 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
> >  	return container_of(nand, struct sunxi_nand_chip, nand);
> >  }
> >
> > +/*
> > + * NAND Controller capabilities structure: stores NAND controller capabilities
> > + * for distinction between compatible strings.
> > + *
> > + * @sram_through_ahb:	On A33, we choose to access the internal RAM through AHB
> > + *                      instead of MBUS (less configuration). A10+ use the MBUS  
> 
> What do you mean by A10+ ?

I meant A1x, A2x SoCs. Not sure it matches a product line for you, so
please suggest something to mean "SoCs which are not A33" (so far I
think all worked without this).

> 
> > + *                      but no extra configuration is needed.
> > + * @reg_io_data:	I/O data register
> > + * @dma_maxburst:	DMA maxburst
> > + */
> > +struct sunxi_nfc_caps {
> > +	bool sram_through_ahb;
> > +	unsigned int reg_io_data;
> > +	unsigned int dma_maxburst;
> > +};  
> 
> Ideally, the introduction of that structure and the introduction of
> the A33 support should be separate patches.

Sure, I can split it up.

> 
> >  /**
> >   * struct sunxi_nfc - stores sunxi NAND controller information
> >   *
> > @@ -228,6 +245,7 @@ struct sunxi_nfc {
> >  	struct list_head chips;
> >  	struct completion complete;
> >  	struct dma_chan *dmac;
> > +	const struct sunxi_nfc_caps *caps;
> >  };
> >
> >  static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_controller *ctrl)
> > @@ -350,10 +368,29 @@ static int sunxi_nfc_dma_op_prepare(struct sunxi_nfc *nfc, const void *buf,
> >  		goto err_unmap_buf;
> >  	}
> >
> > -	writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RAM_METHOD,
> > -	       nfc->regs + NFC_REG_CTL);
> > +	/*
> > +	 * On A33, we suppose the "internal RAM" (p.12 of the user manual)  
> 
> Which user manual? It certainly isn't the A33 user manual :)

You are right it is the A33 NAND flash controller spec.


Thanks,
Miquèl