From: Xiaolei Li <xiaolei.li@mediatek.com>
To: <miquel.raynal@bootlin.com>, <richard@nod.at>
Cc: linux-mediatek@lists.infradead.org, xiaolei.li@mediatek.com,
linux-mtd@lists.infradead.org, srv_heupstream@mediatek.com
Subject: [PATCH 1/5] mtd: rawnand: mtk: Correct low level time calculation of r/w cycle
Date: Mon, 29 Apr 2019 14:38:30 +0800 [thread overview]
Message-ID: <20190429063834.45967-2-xiaolei.li@mediatek.com> (raw)
In-Reply-To: <20190429063834.45967-1-xiaolei.li@mediatek.com>
At present, the flow of calculating AC timing of read/write cycle in SDR
mode is that:
At first, calculate high hold time which is valid for both read and write
cycle using the max value between tREH_min and tWH_min.
Secondly, calculate WE# pulse width using tWP_min.
Thridly, calculate RE# pulse width using the bigger one between tREA_max
and tRP_min.
But NAND SPEC shows that Controller should also meet write/read cycle time.
That is write cycle time should be more than tWC_min and read cycle should
be more than tRC_min. Obviously, we do not achieve that now.
This patch corrects the low level time calculation to meet minimum
read/write cycle time required. After getting the high hold time, WE# low
level time will be promised to meet tWP_min and tWC_min requirement,
and RE# low level time will be promised to meet tREA_max, tRP_min and
tRC_min requirement.
Fixes: 93db446a424c ("mtd: nand: move raw NAND related code to the raw/ subdir")
Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
---
drivers/mtd/nand/raw/mtk_nand.c | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
index b6b4602f5132..dd855f860a4b 100644
--- a/drivers/mtd/nand/raw/mtk_nand.c
+++ b/drivers/mtd/nand/raw/mtk_nand.c
@@ -508,7 +508,7 @@ static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline,
{
struct mtk_nfc *nfc = nand_get_controller_data(chip);
const struct nand_sdr_timings *timings;
- u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt;
+ u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst = 0, trlt = 0;
timings = nand_get_sdr_timings(conf);
if (IS_ERR(timings))
@@ -544,11 +544,19 @@ static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline,
twh = DIV_ROUND_UP(twh * rate, 1000000) - 1;
twh &= 0xf;
- twst = timings->tWP_min / 1000;
+ /* Calculate min low level timing for write cycle */
+ if ((twh + 1) * 1000000 / rate < timings->tWC_min / 1000)
+ twst = (timings->tWC_min / 1000 - (twh + 1) * 1000000 / rate)
+ * 1000;
+ twst = max(timings->tWP_min, twst) / 1000;
twst = DIV_ROUND_UP(twst * rate, 1000000) - 1;
twst &= 0xf;
- trlt = max(timings->tREA_max, timings->tRP_min) / 1000;
+ /* Calculate min low level timing for read cycle */
+ if ((twh + 1) * 1000000 / rate < timings->tRC_min / 1000)
+ trlt = (timings->tRC_min / 1000 - (twh + 1) * 1000000 / rate)
+ * 1000;
+ trlt = max3(trlt, timings->tREA_max, timings->tRP_min) / 1000;
trlt = DIV_ROUND_UP(trlt * rate, 1000000) - 1;
trlt &= 0xf;
--
2.18.0
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next prev parent reply other threads:[~2019-04-29 6:39 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-29 6:38 [PATCH 0/5] MTK NAND driver improvements and fixes Xiaolei Li
2019-04-29 6:38 ` Xiaolei Li [this message]
2019-04-29 9:03 ` [PATCH 1/5] mtd: rawnand: mtk: Correct low level time calculation of r/w cycle Miquel Raynal
2019-04-29 9:35 ` xiaolei li
2019-04-29 10:02 ` Miquel Raynal
2019-04-30 0:59 ` xiaolei li
2019-04-29 6:38 ` [PATCH 2/5] mtd: rawnand: mtk: Improve data sampling timing for read cycle Xiaolei Li
2019-04-29 9:10 ` Miquel Raynal
2019-04-29 9:49 ` xiaolei li
2019-04-29 6:38 ` [PATCH 3/5] mtd: rawnand: mtk: Add validity check for CE# pin setting Xiaolei Li
2019-04-29 9:11 ` Miquel Raynal
2019-04-29 6:38 ` [PATCH 4/5] mtd: rawnand: mtk: Fix wrongly assigned oob buffer pointer issue Xiaolei Li
2019-04-29 9:14 ` Miquel Raynal
2019-04-29 9:52 ` xiaolei li
2019-04-29 6:38 ` [PATCH 5/5] mtd: rawnand: mtk: Setup empty page threshold correctly Xiaolei Li
2019-04-29 9:22 ` Miquel Raynal
2019-04-29 9:57 ` xiaolei li
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