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From: Jungseung Lee <js07.lee@samsung.com>
To: Marek Vasut <marek.vasut@gmail.com>,
	Tudor Ambarus <tudor.ambarus@microchip.com>,
	David Woodhouse <dwmw2@infradead.org>,
	Brian Norris <computersforpeace@gmail.com>,
	Boris Brezillon <bbrezillon@kernel.org>,
	Richard Weinberger <richard@nod.at>,
	u.kleine-koenig@pengutronix.de, linux-mtd@lists.infradead.org,
	js07.lee@gmail.com, js07.lee@samsung.com
Subject: [PATCH v3 4/4] mtd: spi-nor: support lock/unlock for a few Micron chips
Date: Sat, 13 Jul 2019 16:15:41 +0900	[thread overview]
Message-ID: <20190713071541.22090-4-js07.lee@samsung.com> (raw)
In-Reply-To: <20190713071541.22090-1-js07.lee@samsung.com>

Some Micron models are known to have lock/unlock support,
and that also support 4bit block protection bit (bp0-3).

This patch support lock/unlock feature on the flash.

Tested on w25q512ax3. The Other is modified following the datasheet.

Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
---
 drivers/mtd/spi-nor/spi-nor.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 0d0b92de62db..8422f30c73f2 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1922,8 +1922,16 @@ static const struct flash_info spi_nor_ids[] = {
 	{ "n25q128a13",  INFO(0x20ba18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
 	{ "n25q256a",    INFO(0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "n25q256ax1",  INFO(0x20bb19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ) },
-	{ "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
-	{ "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
+	{
+		"n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024,
+			SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
+			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_BP3)
+	},
+	{
+		"n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024,
+			SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
+			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_BP3)
+	},
 	{ "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ "n25q00a",     INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ "mt25qu02g",   INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
-- 
2.17.1


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      parent reply	other threads:[~2019-08-01  2:06 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20190801020509epcas1p155f87090273be705f1a9ae752c0bca5c@epcas1p1.samsung.com>
2019-07-13  7:15 ` [PATCH v3 1/4] mtd: spi-nor: rename SR_TB to indicate the using bit Jungseung Lee
     [not found]   ` <CGME20190801020516epcas1p383452adf9755f7121812aac0f335a779@epcas1p3.samsung.com>
2019-07-13  7:15     ` [PATCH v3 2/4] mtd: spi-nor: introduce SR_BP_SHIFT define Jungseung Lee
     [not found]   ` <CGME20190801020520epcas1p3a9d8fc8175a5cc74be9077c2c6ee678c@epcas1p3.samsung.com>
2019-07-13  7:15     ` [PATCH v3 3/4] mtd: spi-nor: add 4bit block protection support Jungseung Lee
     [not found]   ` <CGME20190801020523epcas1p27580bead294a67fccea6fe8615e73da9@epcas1p2.samsung.com>
2019-07-13  7:15     ` Jungseung Lee [this message]

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