Hi Fabio,

> Hi Lukasz,
> 
> On Mon, Jul 29, 2019 at 6:54 PM Lukasz Majewski <lukma@denx.de> wrote:
> 
> > At best it is possible to have both memories working with double SPI
> > configuration or single (QSPI0_A with quad SPI [2]).  
> 
> But according to
> Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt if you use one
> chip select for bus A and one chip select for bus B, then you should
> have your dts changed like this:
> 
> diff --git a/arch/arm/boot/dts/vf610-bk4.dts
> b/arch/arm/boot/dts/vf610-bk4.dts index 3fa0cbe456db..0f3870d3b099
> 100644 --- a/arch/arm/boot/dts/vf610-bk4.dts
> +++ b/arch/arm/boot/dts/vf610-bk4.dts
> @@ -246,13 +246,13 @@
>                 reg = <0>;
>         };
> 
> -       n25q128a13_2: flash@1 {
> +       n25q128a13_2: flash@2 {
>                 compatible = "n25q128a13", "jedec,spi-nor";
>                 #address-cells = <1>;
>                 #size-cells = <1>;
>                 spi-max-frequency = <66000000>;
>                 spi-rx-bus-width = <2>;
> -               reg = <1>;
> +               reg = <2>;
>         };
>  };

That was the exact issue it seems. I've tested the 5.2. kernel with
this test [1] and it works reliably now.

Apparently those were leftovers from some old, in-house development.

Anyway thanks for help :-)

> 
> From the dt-bindings:
> 
> "Required SPI slave node properties:
>   - reg: There are two buses (A and B) with two chip selects each.
> This encodes to which bus and CS the flash is connected:
> <0>: Bus A, CS 0
> <1>: Bus A, CS 1
> <2>: Bus B, CS 0
> <3>: Bus B, CS 1"


Note:

[1] -
https://github.com/lmajewski/tests-spi/blob/master/tests/spi/spi_nor_quadspi_test.sh

Best regards,

Lukasz Majewski

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