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From: Piotr Sroka <piotrs@cadence.com>
To: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
	devicetree@vger.kernel.org,
	Boris Brezillon <bbrezillon@kernel.org>,
	Richard Weinberger <richard@nod.at>,
	linux-kernel@vger.kernel.org, Marek Vasut <marek.vasut@gmail.com>,
	Rob Herring <robh+dt@kernel.org>,
	linux-mtd@lists.infradead.org,
	BrianNorris <computersforpeace@gmail.com>,
	David Woodhouse <dwmw2@infradead.org>,
	Kazuhiro Kasai <kasai.kazuhiro@socionext.com>
Subject: Re: [v5 2/2] dt-bindings: mtd: Add Cadence NAND controller driver
Date: Fri, 13 Sep 2019 15:41:22 +0100
Message-ID: <20190913144121.GB11985@global.cadence.com> (raw)
In-Reply-To: <20190913144903.0323a23a@xps13>

The 09/13/2019 14:49, Miquel Raynal wrote:
>EXTERNAL MAIL
>
>
>Hi Piotr,
>
>Piotr Sroka <piotrs@cadence.com> wrote on Wed, 11 Sep 2019 16:04:24
>+0100:
>
>> Hi Miquel
>>
>> The 08/30/2019 11:46, Miquel Raynal wrote:
>> >EXTERNAL MAIL
>> >
>> >
>> >Hi Piotr,
>> >
>> >Piotr Sroka <piotrs@cadence.com> wrote on Thu, 25 Jul 2019 15:59:55
>> >+0100:
>> >
>> >> Document the bindings used by Cadence NAND controller driver
>> >>
>> >> Signed-off-by: Piotr Sroka <piotrs@cadence.com>
>> >> ---
>> >> Changes for v5:
>> >> - replace "_" by "-" in all properties
>> >> - change compatible name from cdns,hpnfc to cdns,hp-nfc
>> >> Changes for v4:
>> >> - add commit message
>> >> Changes for v3:
>> >> - add unit suffix for board_delay
>> >> - move child description to proper place
>> >> - remove prefix cadence_ for reg and sdma fields
>> >> Changes for v2:
>> >> - remove chip dependends parameters from dts bindings
>> >> - add names for register ranges in dts bindings
>> >> - add generic bindings to describe NAND chip representation
>> >> ---
>> >>  .../bindings/mtd/cadence-nand-controller.txt       | 50 ++++++++++++++++++++++
>> >>  1 file changed, 50 insertions(+)
>> >>  create mode 100644 Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt
>> >>
>> >> diff --git a/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt b/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt
>> >> new file mode 100644
>> >> index 000000000000..423547a3f993
>> >> --- /dev/null
>> >> +++ b/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt
>> >> @@ -0,0 +1,50 @@
>> >> +* Cadence NAND controller
>> >> +
>> >> +Required properties:
>> >> +  - compatible : "cdns,hp-nfc"
>> >> +  - reg : Contains two entries, each of which is a tuple consisting of a
>> >> +	  physical address and length. The first entry is the address and
>> >> +	  length of the controller register set. The second entry is the
>> >> +	  address and length of the Slave DMA data port.
>> >> +  - reg-names: should contain "reg" and "sdma"
>> >> +  - interrupts : The interrupt number.
>> >> +  - clocks: phandle of the controller core clock (nf_clk).
>> >> +
>> >> +Optional properties:
>> >> +  - dmas: shall reference DMA channel associated to the NAND controller
>> >> +  - cdns,board-delay-ps : Estimated Board delay. The value includes the total
>> >> +    round trip delay for the signals and is used for deciding on values
>> >> +    associated with data read capture. The example formula for SDR mode is
>> >> +    the following:
>> >> +    board delay = RE#PAD delay + PCB trace to device + PCB trace from device
>> >> +    + DQ PAD delay
>> >> +
>> >> +Child nodes represent the available NAND chips.
>> >> +
>> >> +Required properties of NAND chips:
>> >> +  - reg: shall contain the native Chip Select ids from 0 to max supported by
>> >> +    the cadence nand flash controller
>> >> +
>> >> +
>> >> +See Documentation/devicetree/bindings/mtd/nand.txt for more details on
>> >> +generic bindings.
>> >> +
>> >> +Example:
>> >> +
>> >> +nand_controller: nand-controller @60000000 {
>> >> +	  compatible = "cdns,hp-nfc";
>> >> +	  reg = <0x60000000 0x10000>, <0x80000000 0x10000>;
>> >> +	  reg-names = "reg", "sdma";
>> >> +	  clocks = <&nf_clk>;
>> >> +	  cdns,board-delay-ps = <4830>;
>> >
>> >Are you sure you want to export this to the user? Not sure it is easily
>> >understandable and tunable... I'm not against but I would have troubles
>> >tuning it myself, unless using the documented value. Maybe you should
>> >explain more how to derive it?
>> I need to export this parameter somehow. The default value may not be
>> valid for other platforms. This value depends on platform, and may be different on different SoCs. So I think the DTS is the best place to put such configuration
>> parameter.
>
>What about a different compatible if it depends on the SoC?
I considered it but this dealy consists of PADs delay and PCB trace
delay. PAD delays are SoC dependent. Unfortunatelly PCB delay not.
What can I do I can split it on two delays, PAD_delay and trace_delay.
Then handle PAD_delay by compatible and trace_delay by dts. But I am not
sure whether it changes anythig. Still a delay need to passed by dts.
>
>This way you can retrieve a different driver data structure and avoid
>the pain for the user.

>
>Thanks,
>Miquèl


Thanks
Piotr
  

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Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-25 14:58 [v5 0/2] mtd: nand: " Piotr Sroka
2019-07-25 14:59 ` [v5 2/2] dt-bindings: mtd: " Piotr Sroka
2019-08-16 21:31   ` Rob Herring
2019-08-30  9:46   ` Miquel Raynal
2019-09-11 15:04     ` Piotr Sroka
2019-09-13 12:49       ` Miquel Raynal
2019-09-13 14:41         ` Piotr Sroka [this message]
2019-07-25 15:00 ` [v5 1/2] mtd: nand: Add new Cadence NAND driver to MTD subsystem Piotr Sroka
2019-07-25 15:11   ` Dmitry Osipenko
2019-08-24 10:49     ` Miquel Raynal
2019-08-26 15:09       ` Dmitry Osipenko
2019-08-30  9:46   ` Miquel Raynal
2019-09-11  9:43     ` Piotr Sroka
2019-09-11 12:29       ` Miquel Raynal

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