From: "Cédric Le Goater" <clg@kaod.org>
To: linux-mtd@lists.infradead.org,
Tudor Ambarus <tudor.ambarus@microchip.com>
Cc: "Mark Rutland" <mark.rutland@arm.com>,
"Vignesh Raghavendra" <vigneshr@ti.com>,
linux-aspeed@lists.ozlabs.org, "Andrew Jeffery" <andrew@aj.id.au>,
"Richard Weinberger" <richard@nod.at>,
"Marek Vasut" <marek.vasut@gmail.com>,
"Joel Stanley" <joel@jms.id.au>,
"Miquel Raynal" <miquel.raynal@bootlin.com>,
"Brian Norris" <computersforpeace@gmail.com>,
"David Woodhouse" <dwmw2@infradead.org>,
linux-arm-kernel@lists.infradead.org,
"Cédric Le Goater" <clg@kaod.org>
Subject: [PATCH 10/16] mtd: spi-nor: aspeed: Introduce segment operations
Date: Fri, 4 Oct 2019 13:59:13 +0200 [thread overview]
Message-ID: <20191004115919.20788-11-clg@kaod.org> (raw)
In-Reply-To: <20191004115919.20788-1-clg@kaod.org>
AST2600 will use a different encoding for the addresses defined in the
Segment Register.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
---
drivers/mtd/spi-nor/aspeed-smc.c | 78 ++++++++++++++++++++++++--------
1 file changed, 58 insertions(+), 20 deletions(-)
diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c
index c5a0c8d94371..7cdd84a2ca82 100644
--- a/drivers/mtd/spi-nor/aspeed-smc.c
+++ b/drivers/mtd/spi-nor/aspeed-smc.c
@@ -32,6 +32,7 @@ enum aspeed_smc_flash_type {
};
struct aspeed_smc_chip;
+struct aspeed_smc_controller;
struct aspeed_smc_info {
u32 maxsize; /* maximum size of chip window */
@@ -43,6 +44,10 @@ struct aspeed_smc_info {
void (*set_4b)(struct aspeed_smc_chip *chip);
int (*optimize_read)(struct aspeed_smc_chip *chip, u32 max_freq);
+ u32 (*segment_start)(struct aspeed_smc_controller *controller, u32 reg);
+ u32 (*segment_end)(struct aspeed_smc_controller *controller, u32 reg);
+ u32 (*segment_reg)(struct aspeed_smc_controller *controller,
+ u32 start, u32 end);
};
static void aspeed_smc_chip_set_4b_spi_2400(struct aspeed_smc_chip *chip);
@@ -50,6 +55,13 @@ static void aspeed_smc_chip_set_4b(struct aspeed_smc_chip *chip);
static int aspeed_smc_optimize_read(struct aspeed_smc_chip *chip,
u32 max_freq);
+static u32 aspeed_smc_segment_start(struct aspeed_smc_controller *controller,
+ u32 reg);
+static u32 aspeed_smc_segment_end(struct aspeed_smc_controller *controller,
+ u32 reg);
+static u32 aspeed_smc_segment_reg(struct aspeed_smc_controller *controller,
+ u32 start, u32 end);
+
static const struct aspeed_smc_info fmc_2400_info = {
.maxsize = 64 * 1024 * 1024,
.nce = 5,
@@ -59,6 +71,9 @@ static const struct aspeed_smc_info fmc_2400_info = {
.timing = 0x94,
.set_4b = aspeed_smc_chip_set_4b,
.optimize_read = aspeed_smc_optimize_read,
+ .segment_start = aspeed_smc_segment_start,
+ .segment_end = aspeed_smc_segment_end,
+ .segment_reg = aspeed_smc_segment_reg,
};
static const struct aspeed_smc_info spi_2400_info = {
@@ -70,6 +85,7 @@ static const struct aspeed_smc_info spi_2400_info = {
.timing = 0x14,
.set_4b = aspeed_smc_chip_set_4b_spi_2400,
.optimize_read = aspeed_smc_optimize_read,
+ /* No segment registers */
};
static const struct aspeed_smc_info fmc_2500_info = {
@@ -81,6 +97,9 @@ static const struct aspeed_smc_info fmc_2500_info = {
.timing = 0x94,
.set_4b = aspeed_smc_chip_set_4b,
.optimize_read = aspeed_smc_optimize_read,
+ .segment_start = aspeed_smc_segment_start,
+ .segment_end = aspeed_smc_segment_end,
+ .segment_reg = aspeed_smc_segment_reg,
};
static const struct aspeed_smc_info spi_2500_info = {
@@ -92,6 +111,9 @@ static const struct aspeed_smc_info spi_2500_info = {
.timing = 0x94,
.set_4b = aspeed_smc_chip_set_4b,
.optimize_read = aspeed_smc_optimize_read,
+ .segment_start = aspeed_smc_segment_start,
+ .segment_end = aspeed_smc_segment_end,
+ .segment_reg = aspeed_smc_segment_reg,
};
enum aspeed_smc_ctl_reg_value {
@@ -201,22 +223,34 @@ struct aspeed_smc_controller {
(CONTROL_AAF_MODE | CONTROL_CE_INACTIVE_MASK | CONTROL_CLK_DIV4 | \
CONTROL_CLOCK_FREQ_SEL_MASK | CONTROL_LSB_FIRST | CONTROL_CLOCK_MODE_3)
-/*
- * The Segment Register uses a 8MB unit to encode the start address
- * and the end address of the mapping window of a flash SPI slave :
- *
- * | byte 1 | byte 2 | byte 3 | byte 4 |
- * +--------+--------+--------+--------+
- * | end | start | 0 | 0 |
- */
#define SEGMENT_ADDR_REG0 0x30
-#define SEGMENT_ADDR_START(_r) ((((_r) >> 16) & 0xFF) << 23)
-#define SEGMENT_ADDR_END(_r) ((((_r) >> 24) & 0xFF) << 23)
-#define SEGMENT_ADDR_VALUE(start, end) \
- (((((start) >> 23) & 0xFF) << 16) | ((((end) >> 23) & 0xFF) << 24))
#define SEGMENT_ADDR_REG(controller, cs) \
((controller)->regs + SEGMENT_ADDR_REG0 + (cs) * 4)
+/*
+ * The Segment Registers of the AST2400 and AST2500 have a 8MB
+ * unit. The address range of a flash SPI slave is encoded with
+ * absolute addresses which should be part of the overall controller
+ * window.
+ */
+static u32 aspeed_smc_segment_start(struct aspeed_smc_controller *controller,
+ u32 reg)
+{
+ return ((reg >> 16) & 0xFF) << 23;
+}
+
+static u32 aspeed_smc_segment_end(struct aspeed_smc_controller *controller,
+ u32 reg)
+{
+ return ((reg >> 24) & 0xFF) << 23;
+}
+
+static u32 aspeed_smc_segment_reg(struct aspeed_smc_controller *controller,
+ u32 start, u32 end)
+{
+ return (((start >> 23) & 0xFF) << 16) | (((end >> 23) & 0xFF) << 24);
+}
+
/*
* Switch to turn off read optimisation if needed
*/
@@ -519,16 +553,19 @@ static void __iomem *aspeed_smc_chip_base(struct aspeed_smc_chip *chip,
struct resource *res)
{
struct aspeed_smc_controller *controller = chip->controller;
+ const struct aspeed_smc_info *info = controller->info;
u32 offset = 0;
u32 reg;
- if (controller->info->nce > 1) {
+ if (info->nce > 1) {
reg = readl(SEGMENT_ADDR_REG(controller, chip->cs));
- if (SEGMENT_ADDR_START(reg) >= SEGMENT_ADDR_END(reg))
+ if (info->segment_start(controller, reg) >=
+ info->segment_end(controller, reg)) {
return NULL;
+ }
- offset = SEGMENT_ADDR_START(reg) - res->start;
+ offset = info->segment_start(controller, reg) - res->start;
}
return controller->ahb_base + offset;
@@ -538,6 +575,7 @@ static u32 chip_set_segment(struct aspeed_smc_chip *chip, u32 cs, u32 start,
u32 size)
{
struct aspeed_smc_controller *controller = chip->controller;
+ const struct aspeed_smc_info *info = controller->info;
void __iomem *seg_reg;
u32 seg_oldval, seg_newval, end;
u32 ahb_base_phy = controller->ahb_base_phy;
@@ -551,7 +589,7 @@ static u32 chip_set_segment(struct aspeed_smc_chip *chip, u32 cs, u32 start,
* previous segment
*/
if (!size)
- size = SEGMENT_ADDR_END(seg_oldval) - start;
+ size = info->segment_end(controller, seg_oldval) - start;
/*
* The segment cannot exceed the maximum window size of the
@@ -564,7 +602,7 @@ static u32 chip_set_segment(struct aspeed_smc_chip *chip, u32 cs, u32 start,
}
end = start + size;
- seg_newval = SEGMENT_ADDR_VALUE(start, end);
+ seg_newval = info->segment_reg(controller, start, end);
writel(seg_newval, seg_reg);
/*
@@ -575,8 +613,8 @@ static u32 chip_set_segment(struct aspeed_smc_chip *chip, u32 cs, u32 start,
if (seg_newval != readl(seg_reg)) {
dev_err(chip->nor.dev, "CE%d window invalid", cs);
writel(seg_oldval, seg_reg);
- start = SEGMENT_ADDR_START(seg_oldval);
- end = SEGMENT_ADDR_END(seg_oldval);
+ start = info->segment_start(controller, seg_oldval);
+ end = info->segment_end(controller, seg_oldval);
size = end - start;
}
@@ -639,7 +677,7 @@ static u32 aspeed_smc_chip_set_segment(struct aspeed_smc_chip *chip)
if (chip->cs) {
u32 prev = readl(SEGMENT_ADDR_REG(controller, chip->cs - 1));
- start = SEGMENT_ADDR_END(prev);
+ start = controller->info->segment_end(controller, prev);
} else {
start = ahb_base_phy;
}
--
2.21.0
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next prev parent reply other threads:[~2019-10-04 12:06 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-04 11:59 [PATCH 00/16] mtd: spi-nor: aspeed: AST2600 support and extensions Cédric Le Goater
2019-10-04 11:59 ` [PATCH 01/16] mtd: spi-nor: aspeed: Use command mode for reads Cédric Le Goater
2019-10-04 11:59 ` [PATCH 02/16] mtd: spi-nor: aspeed: Add support for SPI dual IO read mode Cédric Le Goater
2019-10-04 11:59 ` [PATCH 03/16] mtd: spi-nor: aspeed: Link controller with the ahb clock Cédric Le Goater
2019-10-04 11:59 ` [PATCH 04/16] mtd: spi-nor: aspeed: Add read training Cédric Le Goater
2019-10-11 12:28 ` Boris Brezillon
2019-10-11 13:13 ` Vignesh Raghavendra
2019-10-11 14:03 ` Cédric Le Goater
2019-10-11 13:55 ` Cédric Le Goater
2019-10-11 14:29 ` Boris Brezillon
2019-10-11 14:37 ` Cédric Le Goater
2019-10-04 11:59 ` [PATCH 05/16] mtd: spi-nor: aspeed: Limit the maximum SPI frequency Cédric Le Goater
2019-10-04 11:59 ` [PATCH 06/16] mtd: spi-nor: fix options for mx66l51235f Cédric Le Goater
2019-10-04 16:23 ` Cédric Le Goater
2019-10-04 11:59 ` [PATCH 07/16] mtd: spi-nor: aspeed: Add support for the 4B opcodes Cédric Le Goater
2019-10-04 11:59 ` [PATCH 08/16] mtd: spi-nor: Add support for w25q512jv Cédric Le Goater
2019-10-04 11:59 ` [PATCH 09/16] mtd: spi-nor: aspeed: Introduce a field for the AHB physical address Cédric Le Goater
2019-10-04 11:59 ` Cédric Le Goater [this message]
2019-10-04 11:59 ` [PATCH 11/16] dt-bindings: mtd: aspeed-smc: Add new comptatible for AST2600 Cédric Le Goater
2019-10-15 19:26 ` Rob Herring
2019-10-04 11:59 ` [PATCH 12/16] mtd: spi-nor: aspeed: Add initial support for the AST2600 Cédric Le Goater
2019-10-04 11:59 ` [PATCH 13/16] mtd: spi-nor: aspeed: Check for disabled segments on " Cédric Le Goater
2019-10-04 12:09 ` [PATCH 14/16] mtd: spi-nor: aspeed: Introduce training operations per platform Cédric Le Goater
2019-10-04 12:09 ` [PATCH 15/16] mtd: spi-nor: aspeed: Introduce a HCLK mask for training Cédric Le Goater
2019-10-04 12:09 ` [PATCH 16/16] mtd: spi-nor: aspeed: Add read training support for the AST2600 Cédric Le Goater
2019-10-09 20:55 ` [PATCH 00/16] mtd: spi-nor: aspeed: AST2600 support and extensions Boris Brezillon
2019-10-10 23:47 ` Joel Stanley
2019-10-11 6:45 ` Boris Brezillon
2019-10-11 9:29 ` Cédric Le Goater
2019-10-11 9:51 ` Boris Brezillon
2019-10-11 11:47 ` Cédric Le Goater
2019-10-11 12:07 ` Boris Brezillon
2019-10-11 13:07 ` Cédric Le Goater
2019-10-11 14:01 ` Boris Brezillon
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