From: <Tudor.Ambarus@microchip.com>
To: <boris.brezillon@collabora.com>, <vigneshr@ti.com>
Cc: richard@nod.at, Tudor.Ambarus@microchip.com,
linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
miquel.raynal@bootlin.com
Subject: [PATCH v4 07/20] mtd: spi-nor: Merge spi_nor_write_sr() and spi_nor_write_sr_cr()
Date: Sat, 2 Nov 2019 11:23:35 +0000 [thread overview]
Message-ID: <20191102112316.20715-8-tudor.ambarus@microchip.com> (raw)
In-Reply-To: <20191102112316.20715-1-tudor.ambarus@microchip.com>
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Merge
static int spi_nor_write_sr(struct spi_nor *nor, u8 val)
static int spi_nor_write_sr_cr(struct spi_nor *nor, const u8 *sr_cr)
into
static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)
The Status Register can be written with one or two bytes. Merge
the two functions to avoid code duplication.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
---
drivers/mtd/spi-nor/spi-nor.c | 74 ++++++++++++++-----------------------------
1 file changed, 23 insertions(+), 51 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index ce32b84f050a..857675a4e329 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -824,16 +824,18 @@ static int spi_nor_wait_till_ready(struct spi_nor *nor)
DEFAULT_READY_WAIT_JIFFIES);
}
-/*
- * Write status register 1 byte
- * Returns negative if error occurred.
+/**
+ * spi_nor_write_sr() - Write the Status Register.
+ * @nor: pointer to 'struct spi_nor'.
+ * @sr: pointer to DMA-able buffer to write to the Status Register.
+ * @len: number of bytes to write to the Status Register.
+ *
+ * Return: 0 on success, -errno otherwise.
*/
-static int spi_nor_write_sr(struct spi_nor *nor, u8 val)
+static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)
{
int ret;
- nor->bouncebuf[0] = val;
-
ret = spi_nor_write_enable(nor);
if (ret)
return ret;
@@ -843,12 +845,12 @@ static int spi_nor_write_sr(struct spi_nor *nor, u8 val)
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1),
SPI_MEM_OP_NO_ADDR,
SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1));
+ SPI_MEM_OP_DATA_OUT(len, sr, 1));
ret = spi_mem_exec_op(nor->spimem, &op);
} else {
ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR,
- nor->bouncebuf, 1);
+ sr, len);
}
if (ret) {
@@ -859,49 +861,15 @@ static int spi_nor_write_sr(struct spi_nor *nor, u8 val)
return spi_nor_wait_till_ready(nor);
}
-/*
- * Write status Register and configuration register with 2 bytes
- * The first byte will be written to the status register, while the
- * second byte will be written to the configuration register.
- * Return negative if error occurred.
- */
-static int spi_nor_write_sr_cr(struct spi_nor *nor, const u8 *sr_cr)
-{
- int ret;
-
- ret = spi_nor_write_enable(nor);
- if (ret)
- return ret;
-
- if (nor->spimem) {
- struct spi_mem_op op =
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1),
- SPI_MEM_OP_NO_ADDR,
- SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_OUT(2, sr_cr, 1));
-
- ret = spi_mem_exec_op(nor->spimem, &op);
- } else {
- ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR,
- sr_cr, 2);
- }
-
- if (ret) {
- dev_dbg(nor->dev,
- "error while writing configuration register\n");
- return -EINVAL;
- }
-
- return spi_nor_wait_till_ready(nor);
-}
-
/* Write status register and ensure bits in mask match written values */
static int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 status_new,
u8 mask)
{
int ret;
- ret = spi_nor_write_sr(nor, status_new);
+ nor->bouncebuf[0] = status_new;
+
+ ret = spi_nor_write_sr(nor, nor->bouncebuf, 1);
if (ret)
return ret;
@@ -1868,7 +1836,9 @@ static int macronix_quad_enable(struct spi_nor *nor)
if (nor->bouncebuf[0] & SR_QUAD_EN_MX)
return 0;
- ret = spi_nor_write_sr(nor, nor->bouncebuf[0] | SR_QUAD_EN_MX);
+ nor->bouncebuf[0] |= SR_QUAD_EN_MX;
+
+ ret = spi_nor_write_sr(nor, nor->bouncebuf, 1);
if (ret)
return ret;
@@ -1915,7 +1885,7 @@ static int spansion_quad_enable(struct spi_nor *nor)
sr_cr[0] = 0;
sr_cr[1] = CR_QUAD_EN_SPAN;
- ret = spi_nor_write_sr_cr(nor, sr_cr);
+ ret = spi_nor_write_sr(nor, sr_cr, 2);
if (ret)
return ret;
@@ -1957,7 +1927,7 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
sr_cr[1] = CR_QUAD_EN_SPAN;
- return spi_nor_write_sr_cr(nor, sr_cr);
+ return spi_nor_write_sr(nor, sr_cr, 2);
}
/**
@@ -1993,7 +1963,7 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
if (ret)
return ret;
- ret = spi_nor_write_sr_cr(nor, sr_cr);
+ ret = spi_nor_write_sr(nor, sr_cr, 2);
if (ret)
return ret;
@@ -2072,7 +2042,9 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor)
if (ret)
return ret;
- return spi_nor_write_sr(nor, nor->bouncebuf[0] & ~mask);
+ nor->bouncebuf[0] &= ~mask;
+
+ return spi_nor_write_sr(nor, nor->bouncebuf, 1);
}
/**
@@ -2110,7 +2082,7 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor)
sr_cr[0] &= ~mask;
- return spi_nor_write_sr_cr(nor, sr_cr);
+ return spi_nor_write_sr(nor, sr_cr, 2);
}
/*
--
2.9.5
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next prev parent reply other threads:[~2019-11-02 11:25 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-02 11:23 [PATCH v4 00/20] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
2019-11-02 11:23 ` [PATCH v4 01/20] mtd: spi-nor: Use dev_dbg insted of dev_err for low level info Tudor.Ambarus
2019-11-05 12:12 ` Vignesh Raghavendra
2019-11-06 7:07 ` Tudor.Ambarus
2019-11-02 11:23 ` [PATCH v4 02/20] mtd: spi-nor: Print debug info inside Reg Ops methods Tudor.Ambarus
2019-11-05 12:13 ` Vignesh Raghavendra
2019-11-02 11:23 ` [PATCH v4 03/20] mtd: spi-nor: Check for errors after each Register Operation Tudor.Ambarus
2019-11-06 9:19 ` Vignesh Raghavendra
2019-11-02 11:23 ` [PATCH v4 04/20] mtd: spi-nor: Rename label as it is no longer generic Tudor.Ambarus
2019-11-02 11:23 ` [PATCH v4 05/20] mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr() Tudor.Ambarus
2019-11-02 11:23 ` [PATCH v4 06/20] mtd: spi-nor: Move the WE and wait calls inside Write SR methods Tudor.Ambarus
2019-11-02 11:23 ` Tudor.Ambarus [this message]
2019-11-02 11:23 ` [PATCH v4 08/20] mtd: spi-nor: Describe all the Reg Ops Tudor.Ambarus
2019-11-05 12:21 ` Vignesh Raghavendra
2019-11-02 11:23 ` [PATCH v4 09/20] mtd: spi-nor: Drop spansion_quad_enable() Tudor.Ambarus
2019-11-05 12:35 ` Vignesh Raghavendra
2019-11-02 11:23 ` [PATCH v4 10/20] mtd: spi-nor: Fix errno on Quad Enable methods Tudor.Ambarus
2019-11-05 12:36 ` Vignesh Raghavendra
2019-11-02 11:23 ` [PATCH v4 11/20] mtd: spi-nor: Check all the bits written, not just the BP ones Tudor.Ambarus
2019-11-05 12:21 ` Vignesh Raghavendra
2019-11-02 11:23 ` [PATCH v4 12/20] mtd: spi-nor: Print debug message when the read back test fails Tudor.Ambarus
2019-11-05 12:37 ` Vignesh Raghavendra
2019-11-06 7:24 ` Tudor.Ambarus
2019-11-06 7:39 ` Vignesh Raghavendra
2019-11-07 5:58 ` Vignesh Raghavendra
2019-11-02 11:23 ` [PATCH v4 13/20] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() Tudor.Ambarus
2019-11-05 17:07 ` Vignesh Raghavendra
2019-11-06 8:33 ` Tudor.Ambarus
2019-11-06 16:26 ` Vignesh Raghavendra
2019-11-02 11:23 ` [PATCH v4 14/20] mtd: spi-nor: Extend the QE Read Back test to the entire SR byte Tudor.Ambarus
2019-11-02 11:23 ` [PATCH v4 15/20] mtd: spi-nor: Extend the QE Read Back test to both SR1 and SR2 Tudor.Ambarus
2019-11-05 16:06 ` Vignesh Raghavendra
2019-11-06 8:41 ` Tudor.Ambarus
2019-11-02 11:23 ` [PATCH v4 16/20] mtd: spi-nor: Rename CR_QUAD_EN_SPAN to SR2_QUAD_EN_BIT1 Tudor.Ambarus
2019-11-06 5:45 ` Vignesh Raghavendra
2019-11-02 11:23 ` [PATCH v4 17/20] mtd: spi-nor: Merge spansion Quad Enable methods Tudor.Ambarus
2019-11-06 5:46 ` Vignesh Raghavendra
2019-11-02 11:23 ` [PATCH v4 18/20] mtd: spi-nor: Rename macronix_quad_enable to spi_nor_sr1_bit6_quad_enable Tudor.Ambarus
2019-11-06 6:00 ` Vignesh Raghavendra
2019-11-02 11:23 ` [PATCH v4 19/20] mtd: spi-nor: Prepend "spi_nor_" to "sr2_bit7_quad_enable" Tudor.Ambarus
2019-11-02 11:24 ` [PATCH v4 20/20] mtd: spi-nor: Rework the disabling of block write protection Tudor.Ambarus
2019-11-07 6:27 ` [PATCH v4 00/20] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
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