From: <Tudor.Ambarus@microchip.com>
To: <boris.brezillon@collabora.com>, <vigneshr@ti.com>
Cc: richard@nod.at, Tudor.Ambarus@microchip.com,
linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
miquel.raynal@bootlin.com
Subject: [PATCH v5 4/6] mtd: spi-nor: Rename CR_QUAD_EN_SPAN to SR2_QUAD_EN_BIT1
Date: Thu, 7 Nov 2019 08:42:01 +0000 [thread overview]
Message-ID: <20191107084135.22122-5-tudor.ambarus@microchip.com> (raw)
In-Reply-To: <20191107084135.22122-1-tudor.ambarus@microchip.com>
From: Tudor Ambarus <tudor.ambarus@microchip.com>
JEDEC Basic Flash Parameter Table, 15th DWORD, bits 22:20,
refers to this bit as "bit 1 of the status register 2".
Rename the macro accordingly.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
---
drivers/mtd/spi-nor/spi-nor.c | 8 ++++----
include/linux/mtd/spi-nor.h | 4 +---
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index d33ad56d3b67..8c59b5220e2a 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1026,7 +1026,7 @@ static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)
* Write Status (01h) command is available just for the cases
* in which the QE bit is described in SR2 at BIT(1).
*/
- sr_cr[1] = CR_QUAD_EN_SPAN;
+ sr_cr[1] = SR2_QUAD_EN_BIT1;
} else {
sr_cr[1] = 0;
}
@@ -2074,7 +2074,7 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
if (ret)
return ret;
- sr_cr[1] = CR_QUAD_EN_SPAN;
+ sr_cr[1] = SR2_QUAD_EN_BIT1;
ret = spi_nor_write_sr(nor, sr_cr, 2);
if (ret)
@@ -2118,10 +2118,10 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
if (ret)
return ret;
- if (sr_cr[1] & CR_QUAD_EN_SPAN)
+ if (sr_cr[1] & SR2_QUAD_EN_BIT1)
return 0;
- sr_cr[1] |= CR_QUAD_EN_SPAN;
+ sr_cr[1] |= SR2_QUAD_EN_BIT1;
/* Keep the current value of the Status Register. */
ret = spi_nor_read_sr(nor, sr_cr);
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 11daecc5a83d..364309845de0 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -144,10 +144,8 @@
#define FSR_P_ERR BIT(4) /* Program operation status */
#define FSR_PT_ERR BIT(1) /* Protection error bit */
-/* Configuration Register bits. */
-#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
-
/* Status Register 2 bits. */
+#define SR2_QUAD_EN_BIT1 BIT(1)
#define SR2_QUAD_EN_BIT7 BIT(7)
/* Supported SPI protocols */
--
2.9.5
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next prev parent reply other threads:[~2019-11-07 8:42 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-07 8:41 [PATCH v5 0/6] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
2019-11-07 8:41 ` [PATCH v5 1/6] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() Tudor.Ambarus
2019-11-07 8:41 ` [PATCH v5 2/6] mtd: spi-nor: Rework the disabling of block write protection Tudor.Ambarus
2019-11-09 9:04 ` Vignesh Raghavendra
2019-11-07 8:41 ` [PATCH v5 3/6] mtd: spi-nor: Extend the SR Read Back test Tudor.Ambarus
2019-11-08 16:03 ` Vignesh Raghavendra
2019-11-07 8:42 ` Tudor.Ambarus [this message]
2019-11-07 8:42 ` [PATCH v5 5/6] mtd: spi-nor: Merge spansion Quad Enable methods Tudor.Ambarus
2019-11-07 8:42 ` [PATCH v5 6/6] mtd: spi-nor: Rename " Tudor.Ambarus
2019-11-08 16:02 ` Vignesh Raghavendra
2019-11-11 19:26 ` [PATCH v5 0/6] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
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