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* [PATCH v2] mtd: spi-nor: Add support for w25q32jwm
@ 2020-01-16 15:42 Michael Walle
  2020-01-19  7:19 ` Tudor.Ambarus
  0 siblings, 1 reply; 2+ messages in thread
From: Michael Walle @ 2020-01-16 15:42 UTC (permalink / raw)
  To: linux-mtd, linux-kernel
  Cc: Richard Weinberger, Michael Walle, Miquel Raynal,
	Vignesh Raghavendra, Tudor Ambarus

Add support for the Winbond W25Q32JW-xM flashes. These have a
programmable QE bit. There is also the W25Q32JW-xQ variant which shares
the ID with the W25Q32DW and W25Q32FW parts. The W25Q32JW-xQ has the QE
bit hard strapped to 1, thus don't support the /HOLD and /WP pins.

This was tested in single, dual and quad mode on a custom board with the
NXP FlexSPI controller. Also the BP bits as well as the TB bit were
tested.

Signed-off-by: Michael Walle <michael@walle.cc>
---
This patch superseeds the following patch:
  https://lore.kernel.org/linux-mtd/20200103223423.14025-1-michael@walle.cc/

changes since v1:
 - renamed flash to w25q32jwm
 - removed untested flashes
 - reworded the commit message

 drivers/mtd/spi-nor/spi-nor.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index d09a9e38d0bc..8226d6450069 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -2651,6 +2651,11 @@ static const struct flash_info spi_nor_ids[] = {
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
 	},
+	{
+		"w25q32jwm", INFO(0xef8016, 0, 64 * 1024,  64,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+	},
 	{ "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
 	{ "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
 	{
-- 
2.20.1


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^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH v2] mtd: spi-nor: Add support for w25q32jwm
  2020-01-16 15:42 [PATCH v2] mtd: spi-nor: Add support for w25q32jwm Michael Walle
@ 2020-01-19  7:19 ` Tudor.Ambarus
  0 siblings, 0 replies; 2+ messages in thread
From: Tudor.Ambarus @ 2020-01-19  7:19 UTC (permalink / raw)
  To: linux-mtd; +Cc: vigneshr, richard, michael, linux-kernel, miquel.raynal

On Thursday, January 16, 2020 5:42:09 PM EET Michael Walle wrote:
> Add support for the Winbond W25Q32JW-xM flashes. These have a
> programmable QE bit. There is also the W25Q32JW-xQ variant which shares
> the ID with the W25Q32DW and W25Q32FW parts. The W25Q32JW-xQ has the QE
> bit hard strapped to 1, thus don't support the /HOLD and /WP pins.
> 
> This was tested in single, dual and quad mode on a custom board with the
> NXP FlexSPI controller. Also the BP bits as well as the TB bit were
> tested.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
> This patch superseeds the following patch:
>   https://lore.kernel.org/linux-mtd/20200103223423.14025-1-michael@walle.cc/
> 
> changes since v1:
>  - renamed flash to w25q32jwm
>  - removed untested flashes
>  - reworded the commit message
> 
>  drivers/mtd/spi-nor/spi-nor.c | 5 +++++
>  1 file changed, 5 insertions(+)

Applied to spi-nor/next. Thanks.
ta


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^ permalink raw reply	[flat|nested] 2+ messages in thread

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2020-01-16 15:42 [PATCH v2] mtd: spi-nor: Add support for w25q32jwm Michael Walle
2020-01-19  7:19 ` Tudor.Ambarus

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