From: Miquel Raynal <miquel.raynal@bootlin.com>
To: shiva.linuxworks@gmail.com
Cc: Vignesh Raghavendra <vigneshr@ti.com>,
Boris Brezillon <bbrezillon@kernel.org>,
Richard Weinberger <richard@nod.at>,
linux-kernel@vger.kernel.org,
Frieder Schrempf <frieder.schrempf@kontron.de>,
linux-mtd@lists.infradead.org,
Shivamurthy Shastri <sshivamurthy@micron.com>
Subject: Re: [PATCH v3 4/5] mtd: spinand: micron: Add M70A series Micron SPI NAND devices
Date: Wed, 5 Feb 2020 10:54:22 +0100 [thread overview]
Message-ID: <20200205105422.57b5f6c4@xps13> (raw)
In-Reply-To: <20200202215508.2928-5-sshivamurthy@micron.com>
Hi shiva.linuxworks@gmail.com,
shiva.linuxworks@gmail.com wrote on Sun, 2 Feb 2020 22:55:07 +0100:
> From: Shivamurthy Shastri <sshivamurthy@micron.com>
>
> Add device table for M70A series Micron SPI NAND devices.
>
> As opposed to the M79A and M78A series already supported, M70A parts
> have the "Continuous Read" feature enabled by default, which does not fit
> the subsystem needs.
>
> In this mode, the READ CACHE command doesn't require the starting column
> address. The device always output the data starting from the first
> column of the cache register, and once the end of the cache register
> reached, the data output continues through the next page. With the
> continuous read mode, it is possible to read out the entire block using
> a single READ command, and once the end of the block reached, the output
> pins become High-Z state. However, during this mode the read command
> doesn't output the OOB area.
>
> Hence, we disable the feature at probe time.
>
> Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com>
> ---
> drivers/mtd/nand/spi/micron.c | 36 +++++++++++++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
> index 5fd1f921ef12..3d3734afc35e 100644
> --- a/drivers/mtd/nand/spi/micron.c
> +++ b/drivers/mtd/nand/spi/micron.c
> @@ -18,6 +18,8 @@
> #define MICRON_STATUS_ECC_4TO6_BITFLIPS (3 << 4)
> #define MICRON_STATUS_ECC_7TO8_BITFLIPS (5 << 4)
>
> +#define MICRON_CFG_CONTI_READ BIT(0)
> +
> static SPINAND_OP_VARIANTS(read_cache_variants,
> SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
> SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
> @@ -131,6 +133,26 @@ static const struct spinand_info micron_spinand_table[] = {
> 0,
> SPINAND_ECCINFO(µn_8_ooblayout,
> micron_8_ecc_get_status)),
> + /* M70A 4Gb 3.3V */
> + SPINAND_INFO("MT29F4G01ABAFD", 0x34,
> + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
> + NAND_ECCREQ(8, 512),
> + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> + &write_cache_variants,
> + &update_cache_variants),
> + SPINAND_HAS_CR_FEAT_BIT,
> + SPINAND_ECCINFO(µn_8_ooblayout,
> + micron_8_ecc_get_status)),
> + /* M70A 4Gb 1.8V */
> + SPINAND_INFO("MT29F4G01ABBFD", 0x35,
> + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
> + NAND_ECCREQ(8, 512),
> + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> + &write_cache_variants,
> + &update_cache_variants),
> + SPINAND_HAS_CR_FEAT_BIT,
> + SPINAND_ECCINFO(µn_8_ooblayout,
> + micron_8_ecc_get_status)),
> };
>
> static int micron_spinand_detect(struct spinand_device *spinand)
> @@ -153,8 +175,22 @@ static int micron_spinand_detect(struct spinand_device *spinand)
> return 1;
> }
>
> +static int micron_spinand_init(struct spinand_device *spinand)
> +{
> + /*
> + * M70A device series enable Continuous Read feature at Power-up,
> + * which is not supported. Disable this bit to avoid any possible
> + * failure.
> + */
> + if (spinand->flags == SPINAND_HAS_CR_FEAT_BIT)
> + return spinand_upd_cfg(spinand, MICRON_CFG_CONTI_READ, 0);
> +
> + return 0;
> +}
> +
> static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = {
> .detect = micron_spinand_detect,
> + .init = micron_spinand_init,
> };
I would move the addition of .init = ... and the function definition to
patch 3/5.
The logic is:
1/ You introduce the feature
2/ You add support for new devices and use this feature
>
> const struct spinand_manufacturer micron_spinand_manufacturer = {
Otherwise looks good.
Thanks,
Miquèl
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2020-02-05 9:54 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-02 21:55 [PATCH v3 0/5] Add new series Micron SPI NAND devices shiva.linuxworks
2020-02-02 21:55 ` [PATCH v3 1/5] mtd: spinand: micron: Generalize the OOB layout structure and function names shiva.linuxworks
2020-02-02 21:55 ` [PATCH v3 2/5] mtd: spinand: micron: Add new Micron SPI NAND devices shiva.linuxworks
2020-02-02 21:55 ` [PATCH v3 3/5] mtd: spinand: identfiy SPI NAND device with Continuous Read mode shiva.linuxworks
2020-02-02 21:55 ` [PATCH v3 4/5] mtd: spinand: micron: Add M70A series Micron SPI NAND devices shiva.linuxworks
2020-02-05 9:54 ` Miquel Raynal [this message]
2020-02-02 21:55 ` [PATCH v3 5/5] mtd: spinand: micron: Add new Micron SPI NAND devices with multiple dies shiva.linuxworks
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200205105422.57b5f6c4@xps13 \
--to=miquel.raynal@bootlin.com \
--cc=bbrezillon@kernel.org \
--cc=frieder.schrempf@kontron.de \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mtd@lists.infradead.org \
--cc=richard@nod.at \
--cc=shiva.linuxworks@gmail.com \
--cc=sshivamurthy@micron.com \
--cc=vigneshr@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).