From: Jungseung Lee <js07.lee@samsung.com>
To: Tudor Ambarus <tudor.ambarus@microchip.com>,
Vignesh Raghavendra <vigneshr@ti.com>,
linux-mtd@lists.infradead.org, js07.lee@gmail.com,
chenxiang <chenxiang66@hisilicon.com>,
Michael Walle <michael@walle.cc>,
John Garry <john.garry@huawei.com>,
js07.lee@samsung.com
Subject: [PATCH v2 3/3] mtd: spi-nor: support lock/unlock for a few Micron chips
Date: Wed, 18 Mar 2020 21:06:15 +0900 [thread overview]
Message-ID: <20200318120615.4639-3-js07.lee@samsung.com> (raw)
In-Reply-To: <20200318120615.4639-1-js07.lee@samsung.com>
Some Micron models are known to have lock/unlock support,
and that also support 4bit block protection (bp0-3).
This patch support lock/unlock feature on the flashes.
Tested on n25q512ax3. The other is modified following the datasheet.
Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
---
drivers/mtd/spi-nor/micron-st.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 3874a62d8b47..6c034b9718e2 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -47,12 +47,16 @@ static const struct flash_info st_parts[] = {
SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024,
- SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
+ SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
+ SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) },
{ "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024,
SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024,
- SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
+ SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
+ SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) },
{ "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048,
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
NO_CHIP_ERASE) },
--
2.17.1
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next prev parent reply other threads:[~2020-03-18 12:08 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20200318120801epcas1p3845986eadf5f4aea47233f71e4e60508@epcas1p3.samsung.com>
2020-03-18 12:06 ` [PATCH v2 1/3] mtd: spi-nor: reimplement block protection handling Jungseung Lee
[not found] ` <CGME20200318120803epcas1p34570b795db84b2fd429b299a9ab317bd@epcas1p3.samsung.com>
2020-03-18 12:06 ` [PATCH v2 2/3] mtd: spi-nor: add 4bit block protection support Jungseung Lee
2020-03-21 20:47 ` Michael Walle
[not found] ` <CGME20200318120804epcas1p37b89db641c44ac84a778447bc6d7fbf2@epcas1p3.samsung.com>
2020-03-18 12:06 ` Jungseung Lee [this message]
2020-03-21 20:48 ` [PATCH v2 1/3] mtd: spi-nor: reimplement block protection handling Michael Walle
2020-01-13 5:37 [PATCH v2 1/3] mtd: spi-nor: introduce SR_BP_SHIFT define Jungseung Lee
[not found] ` <CGME20200113053757epcas1p343bae16b96761ee4ead6bdfc6712ad68@epcas1p3.samsung.com>
2020-01-13 5:37 ` [PATCH v2 3/3] mtd: spi-nor: support lock/unlock for a few Micron chips Jungseung Lee
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