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Thu, 19 Mar 2020 11:44:52 -0700 (PDT) Received: from rob-hp-laptop ([64.188.179.250]) by smtp.gmail.com with ESMTPSA id s69sm1150358ill.73.2020.03.19.11.44.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Mar 2020 11:44:51 -0700 (PDT) Received: (nullmailer pid 10183 invoked by uid 1000); Thu, 19 Mar 2020 18:44:48 -0000 Date: Thu, 19 Mar 2020 12:44:48 -0600 From: Rob Herring To: "Ramuthevar, Vadivel MuruganX" Subject: Re: [PATCH v12 1/4] dt-bindings: spi: Add schema for Cadence QSPI Controller driver Message-ID: <20200319184448.GA25121@bogus> References: <20200310015213.1734-1-vadivel.muruganx.ramuthevar@linux.intel.com> <20200310015213.1734-2-vadivel.muruganx.ramuthevar@linux.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200310015213.1734-2-vadivel.muruganx.ramuthevar@linux.intel.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200319_114453_279855_2AD878F5 X-CRM114-Status: GOOD ( 25.01 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, devicetree@vger.kernel.org, tien.fong.chee@intel.com, tudor.ambarus@gmail.com, vigneshr@ti.com, boris.brezillon@free-electrons.com, richard@nod.at, qi-ming.wu@intel.com, simon.k.r.goldschmidt@gmail.com, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, dinguyen@kernel.org, broonie@kernel.org, linux-mtd@lists.infradead.org, miquel.raynal@bootlin.com, cheol.yong.kim@intel.com, cyrille.pitchen@atmel.com, computersforpeace@gmail.com, dwmw2@infradead.org, david.oberhollenzer@sigma-star.at Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org On Tue, Mar 10, 2020 at 09:52:10AM +0800, Ramuthevar,Vadivel MuruganX wrote: > From: Ramuthevar Vadivel Murugan > > Add dt-bindings documentation for Cadence-QSPI controller to support > spi based flash memories. > > Signed-off-by: Ramuthevar Vadivel Murugan > --- > .../devicetree/bindings/mtd/cadence-quadspi.txt | 67 ----------- > .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 127 +++++++++++++++++++++ > 2 files changed, 127 insertions(+), 67 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt > create mode 100644 Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml > > diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt > deleted file mode 100644 > index 945be7d5b236..000000000000 > --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt > +++ /dev/null > @@ -1,67 +0,0 @@ > -* Cadence Quad SPI controller > - > -Required properties: > -- compatible : should be one of the following: > - Generic default - "cdns,qspi-nor". > - For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". > - For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor". > -- reg : Contains two entries, each of which is a tuple consisting of a > - physical address and length. The first entry is the address and > - length of the controller register set. The second entry is the > - address and length of the QSPI Controller data area. > -- interrupts : Unit interrupt specifier for the controller interrupt. > -- clocks : phandle to the Quad SPI clock. > -- cdns,fifo-depth : Size of the data FIFO in words. > -- cdns,fifo-width : Bus width of the data FIFO in bytes. > -- cdns,trigger-address : 32-bit indirect AHB trigger address. > - > -Optional properties: > -- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not. > -- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch > - the read data rather than the QSPI clock. Make sure that QSPI return > - clock is populated on the board before using this property. > - > -Optional subnodes: > -Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional > -custom properties: > -- cdns,read-delay : Delay for read capture logic, in clock cycles > -- cdns,tshsl-ns : Delay in nanoseconds for the length that the master > - mode chip select outputs are de-asserted between > - transactions. > -- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being > - de-activated and the activation of another. > -- cdns,tchsh-ns : Delay in nanoseconds between last bit of current > - transaction and deasserting the device chip select > - (qspi_n_ss_out). > -- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low > - and first bit transfer. > -- resets : Must contain an entry for each entry in reset-names. > - See ../reset/reset.txt for details. > -- reset-names : Must include either "qspi" and/or "qspi-ocp". > - > -Example: > - > - qspi: spi@ff705000 { > - compatible = "cdns,qspi-nor"; > - #address-cells = <1>; > - #size-cells = <0>; > - reg = <0xff705000 0x1000>, > - <0xffa00000 0x1000>; > - interrupts = <0 151 4>; > - clocks = <&qspi_clk>; > - cdns,is-decoded-cs; > - cdns,fifo-depth = <128>; > - cdns,fifo-width = <4>; > - cdns,trigger-address = <0x00000000>; > - resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>; > - reset-names = "qspi", "qspi-ocp"; > - > - flash0: n25q00@0 { > - ... > - cdns,read-delay = <4>; > - cdns,tshsl-ns = <50>; > - cdns,tsd2d-ns = <50>; > - cdns,tchsh-ns = <4>; > - cdns,tslch-ns = <4>; > - }; > - }; > diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml > new file mode 100644 > index 000000000000..d21f80604af4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml > @@ -0,0 +1,127 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Cadence QSPI Flash Controller support > + > +maintainers: > + - Ramuthevar Vadivel Murugan > + > +allOf: > + - $ref: "spi-controller.yaml#" > + > +description: | > + Binding Documentation for Cadence QSPI controller,This controller is > + present in the Intel LGM, Altera SoCFPGA and TI SoCs and this driver > + has been tested On Intel's LGM SoC. > + > +properties: > + compatible: > + enum: > + - cdns,qspi-nor > + - ti,k2g-qspi > + - ti,am654-ospi > + - intel,lgm-qspi > + > + reg: > + maxItems: 2 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + cdns,fifo-depth: > + description: > + Depth of hardware FIFOs. > + allOf: > + - $ref: "/schemas/types.yaml#/definitions/uint32" > + - enum: [ 128, 256 ] > + - default: 128 > + > + cdns,fifo-width: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + 4 byte bus width of the data FIFO in bytes. > + > + cdns,trigger-address: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + 32-bit indirect AHB trigger address. > + > + cdns,rclk-en: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: | > + Flag to indicate that QSPI return clock is used to latch the read data > + rather than the QSPI clock. Make sure that QSPI return clock is populated > + on the board before using this property. Sounds like a boolean rather than a uint32? If not, then constraints on the values? > +# subnode's properties > +patternProperties: > + "^.*@[0-9a-fA-F]+$": How many chip selects do you support? The unit-address can be limited as I'd guess it's less than 16. Also, should be lowercase hex. > + type: object > + description: > + flash device uses the subnodes below defined properties. > + > + cdns,read-delay: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + Delay in 4 microseconds, read capture logic, in clock cycles. 4us or clock cycles? > + > + cdns,tshsl-ns: > + description: | > + Delay in 50 nanoseconds, for the length that the master mode chip select > + outputs are de-asserted between transactions. Sounds like you can add: multipleOf: 50 > + > + cdns,tsd2d-ns: > + description: | > + Delay in 50 nanoseconds, between one chip select being de-activated > + and the activation of another. Same here > + > + cdns,tchsh-ns: > + description: | > + Delay in 4 nanoseconds, between last bit of current transaction and > + deasserting the device chip select (qspi_n_ss_out). multipleOf: 4 > + > + cdns,tslch-ns: > + description: | > + Delay in 4 nanoseconds, between setting qspi_n_ss_out low and > + first bit transfer. multipleOf: 4 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - cdns,fifo-depth > + - cdns,fifo-width > + - cdns,trigger-address > + > +examples: > + - | > + qspi: spi@ff705000 { Drop the label. > + compatible = "cdns,qspi-nor"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0xff705000 0x1000>, > + <0xffa00000 0x1000>; > + interrupts = <0 151 4>; > + clocks = <&qspi_clk>; > + cdns,fifo-depth = <128>; > + cdns,fifo-width = <4>; > + cdns,trigger-address = <0x00000000>; > + > + flash0: n25q00@0 { flash@0 > + compatible = "jedec,spi-nor"; > + reg = <0x0>; > + cdns,read-delay = <4>; > + cdns,tshsl-ns = <50>; > + cdns,tsd2d-ns = <50>; > + cdns,tchsh-ns = <4>; > + cdns,tslch-ns = <4>; > + }; > + }; > + > -- > 2.11.0 > ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/