From: Pratyush Yadav <p.yadav@ti.com>
To: Tudor Ambarus <tudor.ambarus@microchip.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Mark Brown <broonie@kernel.org>,
Nicolas Ferre <nicolas.ferre@microchip.com>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
Ludovic Desroches <ludovic.desroches@microchip.com>,
<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
<linux-spi@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Cc: Sekhar Nori <nsekhar@ti.com>, Pratyush Yadav <p.yadav@ti.com>
Subject: [PATCH v4 11/16] mtd: spi-nor: enable octal DTR mode when possible
Date: Sat, 25 Apr 2020 00:14:05 +0530 [thread overview]
Message-ID: <20200424184410.8578-12-p.yadav@ti.com> (raw)
In-Reply-To: <20200424184410.8578-1-p.yadav@ti.com>
Allow flashes to specify a hook to enable octal DTR mode. Use this hook
whenever possible to get optimal transfer speeds.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
---
drivers/mtd/spi-nor/core.c | 35 +++++++++++++++++++++++++++++++++++
drivers/mtd/spi-nor/core.h | 2 ++
2 files changed, 37 insertions(+)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 6eb2b1781972..c75765f09d62 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -3085,6 +3085,35 @@ static int spi_nor_init_params(struct spi_nor *nor)
return 0;
}
+/** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
+ * @nor: pointer to a 'struct spi_nor'
+ * @enable: whether to enable or disable Octal DTR
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_octal_dtr_enable(struct spi_nor *nor, bool enable)
+{
+ int ret;
+
+ if (!nor->params->octal_dtr_enable)
+ return 0;
+
+ if (!(spi_nor_get_protocol_width(nor->read_proto) == 8 ||
+ spi_nor_get_protocol_width(nor->write_proto) == 8))
+ return 0;
+
+ ret = nor->params->octal_dtr_enable(nor, enable);
+ if (ret)
+ return ret;
+
+ if (enable)
+ nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
+ else
+ nor->reg_proto = SNOR_PROTO_1_1_1;
+
+ return 0;
+}
+
/**
* spi_nor_quad_enable() - enable Quad I/O if needed.
* @nor: pointer to a 'struct spi_nor'
@@ -3124,6 +3153,12 @@ static int spi_nor_init(struct spi_nor *nor)
{
int err;
+ err = spi_nor_octal_dtr_enable(nor, true);
+ if (err) {
+ dev_dbg(nor->dev, "octal mode not supported\n");
+ return err;
+ }
+
err = spi_nor_quad_enable(nor);
if (err) {
dev_dbg(nor->dev, "quad mode not supported\n");
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 7e6df8322da0..6338d32a0d77 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -203,6 +203,7 @@ struct spi_nor_locking_ops {
* higher index in the array, the higher priority.
* @erase_map: the erase map parsed from the SFDP Sector Map Parameter
* Table.
+ * @octal_dtr_enable: enables SPI NOR octal DTR mode.
* @quad_enable: enables SPI NOR quad mode.
* @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode.
* @convert_addr: converts an absolute address into something the flash
@@ -226,6 +227,7 @@ struct spi_nor_flash_parameter {
struct spi_nor_erase_map erase_map;
+ int (*octal_dtr_enable)(struct spi_nor *nor, bool enable);
int (*quad_enable)(struct spi_nor *nor);
int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable);
u32 (*convert_addr)(struct spi_nor *nor, u32 addr);
--
2.25.0
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next prev parent reply other threads:[~2020-04-24 18:52 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-24 18:43 [PATCH v4 00/16] mtd: spi-nor: add xSPI Octal DTR support Pratyush Yadav
2020-04-24 18:43 ` [PATCH v4 01/16] spi: spi-mem: allow specifying whether an op is DTR or not Pratyush Yadav
2020-04-24 18:43 ` [PATCH v4 02/16] spi: atmel-quadspi: reject DTR ops Pratyush Yadav
2020-04-30 11:32 ` Mark Brown
2020-04-30 12:17 ` Pratyush Yadav
2020-04-30 12:19 ` Mark Brown
2020-04-24 18:43 ` [PATCH v4 03/16] spi: spi-mem: allow specifying a command's extension Pratyush Yadav
2020-04-24 18:43 ` [PATCH v4 04/16] mtd: spi-nor: add support for DTR protocol Pratyush Yadav
2020-04-24 18:43 ` [PATCH v4 05/16] mtd: spi-nor: default to address width of 3 for configurable widths Pratyush Yadav
2020-04-26 3:53 ` Yicong Yang
2020-04-27 17:23 ` Pratyush Yadav
2020-04-28 1:34 ` Yicong Yang
2020-04-28 5:25 ` Tudor.Ambarus
2020-04-24 18:44 ` [PATCH v4 06/16] mtd: spi-nor: prepare BFPT parsing for JESD216 rev D Pratyush Yadav
2020-04-24 18:44 ` [PATCH v4 07/16] mtd: spi-nor: get command opcode extension type from BFPT Pratyush Yadav
2020-04-24 18:44 ` [PATCH v4 08/16] mtd: spi-nor: parse xSPI Profile 1.0 table Pratyush Yadav
2020-04-24 18:44 ` [PATCH v4 09/16] mtd: spi-nor: use dummy cycle and address width info from SFDP Pratyush Yadav
2020-04-24 18:44 ` [PATCH v4 10/16] mtd: spi-nor: do 2 byte reads for SR and FSR in DTR mode Pratyush Yadav
2020-04-24 18:44 ` Pratyush Yadav [this message]
2020-04-24 18:44 ` [PATCH v4 12/16] mtd: spi-nor: perform a Soft Reset on shutdown Pratyush Yadav
2020-05-10 11:22 ` Tudor.Ambarus
2020-05-11 18:01 ` Pratyush Yadav
2020-04-24 18:44 ` [PATCH v4 13/16] mtd: spi-nor: Disable Octal DTR mode on suspend Pratyush Yadav
2020-04-24 18:44 ` [PATCH v4 14/16] mtd: spi-nor: expose spi_nor_default_setup() in core.h Pratyush Yadav
2020-04-24 18:44 ` [PATCH v4 15/16] mtd: spi-nor: add support for Cypress Semper flash Pratyush Yadav
2020-04-24 18:44 ` [PATCH v4 16/16] mtd: spi-nor: allow using MT35XU512ABA in Octal DTR mode Pratyush Yadav
2020-05-11 9:00 ` [PATCH v4 00/16] mtd: spi-nor: add xSPI Octal DTR support Tudor.Ambarus
2020-05-11 9:27 ` Boris Brezillon
2020-05-11 18:24 ` Pratyush Yadav
2020-05-12 6:16 ` Tudor.Ambarus
2020-05-12 9:49 ` Vignesh Raghavendra
2020-05-12 11:29 ` Tudor.Ambarus
2020-05-12 18:46 ` Pratyush Yadav
2020-05-11 9:43 ` Vignesh Raghavendra
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