From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>, <devicetree@vger.kernel.org>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Tudor Ambarus <Tudor.Ambarus@microchip.com>,
<linux-mtd@lists.infradead.org>
Cc: Michal Simek <monstr@monstr.eu>,
Boris Brezillon <boris.brezillon@collabora.com>,
Naga Sureshkumar Relli <nagasure@xilinx.com>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Miquel Raynal <miquel.raynal@bootlin.com>
Subject: [PATCH v4 4/8] mtd: rawnand: Add nand_extract_bits()
Date: Fri, 8 May 2020 19:13:35 +0200 [thread overview]
Message-ID: <20200508171339.8052-5-miquel.raynal@bootlin.com> (raw)
In-Reply-To: <20200508171339.8052-1-miquel.raynal@bootlin.com>
There are cases where ECC bytes are not byte-aligned. Indeed, BCH
implies using a number of ECC bits, which are not always a multiple of
8. We then need a helper like nand_extract_bits() to extract these
syndromes from a buffer.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/raw/nand_base.c | 42 ++++++++++++++++++++++++++++++++
include/linux/mtd/rawnand.h | 4 +++
2 files changed, 46 insertions(+)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 25d298938aa9..d3b3b929e038 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -224,6 +224,48 @@ static int check_offs_len(struct nand_chip *chip, loff_t ofs, uint64_t len)
return ret;
}
+/** nand_extract_bits - Copy unaligned bits from one buffer to another one
+ * @dst: destination buffer
+ * @dst_off: bit offset at which the writing starts
+ * @src: source buffer
+ * @src_off: bit offset at which the reading starts
+ * @nbits: number of bits to copy from @src to @dst
+ *
+ * Copy bits from one memory region to another (overlap authorized).
+ */
+void nand_extract_bits(u8 *dst, unsigned int dst_off, const u8 *src,
+ unsigned int src_off, unsigned int nbits)
+{
+ unsigned int tmp, n;
+
+ dst += dst_off / 8;
+ dst_off %= 8;
+ src += src_off / 8;
+ src_off %= 8;
+
+ while (nbits) {
+ n = min3(8 - dst_off, 8 - src_off, nbits);
+
+ tmp = (*src >> src_off) & GENMASK(n - 1, 0);
+ *dst &= ~GENMASK(n - 1 + dst_off, dst_off);
+ *dst |= tmp << dst_off;
+
+ dst_off += n;
+ if (dst_off >= 8) {
+ dst++;
+ dst_off -= 8;
+ }
+
+ src_off += n;
+ if (src_off >= 8) {
+ src++;
+ src_off -= 8;
+ }
+
+ nbits -= n;
+ }
+}
+
/**
* nand_select_target() - Select a NAND target (A.K.A. die)
* @chip: NAND chip object
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 406e9ff0f45c..8159bd818536 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -1404,6 +1404,10 @@ int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod,
void nand_select_target(struct nand_chip *chip, unsigned int cs);
void nand_deselect_target(struct nand_chip *chip);
+/* Bitops */
+void nand_extract_bits(u8 *dst, unsigned int dst_off, const u8 *src,
+ unsigned int src_off, unsigned int nbits);
+
/**
* nand_get_data_buf() - Get the internal page buffer
* @chip: NAND chip object
--
2.20.1
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next prev parent reply other threads:[~2020-05-08 17:14 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-08 17:13 [PATCH v4 0/8] New Arasan NAND controller driver Miquel Raynal
2020-05-08 17:13 ` [PATCH v4 1/8] lib/bch: Rework a little bit the exported function names Miquel Raynal
2020-05-08 17:13 ` [PATCH v4 2/8] lib/bch: Allow easy bit swapping Miquel Raynal
2020-05-08 17:13 ` [PATCH v4 3/8] mtd: rawnand: Ensure the number of bitflips is consistent Miquel Raynal
2020-05-08 17:13 ` Miquel Raynal [this message]
2020-05-08 17:13 ` [PATCH v4 5/8] MAINTAINERS: Add Arasan NAND controller and bindings Miquel Raynal
2020-05-08 17:13 ` [PATCH v4 6/8] dt-bindings: mtd: Document ARASAN NAND bindings Miquel Raynal
2020-05-11 14:10 ` Michal Simek
2020-05-18 18:12 ` Rob Herring
2020-05-08 17:13 ` [PATCH v4 7/8] mtd: rawnand: arasan: Add new Arasan NAND controller Miquel Raynal
2020-05-10 6:51 ` Boris Brezillon
2020-05-10 6:52 ` Boris Brezillon
2020-05-10 8:33 ` Miquel Raynal
2020-05-10 7:02 ` Boris Brezillon
2020-05-10 8:35 ` Miquel Raynal
2020-05-10 8:41 ` Boris Brezillon
2020-05-10 8:53 ` Miquel Raynal
2020-05-11 16:14 ` Miquel Raynal
2020-05-10 7:03 ` Boris Brezillon
2020-05-11 15:07 ` Miquel Raynal
2020-05-11 15:32 ` Boris Brezillon
2020-05-11 15:46 ` Miquel Raynal
2020-05-11 15:50 ` Miquel Raynal
2020-05-11 15:59 ` Boris Brezillon
2020-05-08 17:13 ` [PATCH v4 8/8] mtd: rawnand: arasan: Support the hardware BCH ECC engine Miquel Raynal
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